riscv/rocket-chip
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go back to using standard LockingArbiter

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This commit is contained in:
Howard Mao 2015-10-21 09:15:51 -07:00
parent c68d9f8137
commit 0b7c828b5d
1 changed files with 2 additions and 2 deletions
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4
rocket/src/main/scala/nbdcache.scala
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@ -405,7 +405,7 @@ class MSHRFile(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val refillMux = Wire(Vec(new L1RefillReq, nMSHRs)) val refillMux = Wire(Vec(new L1RefillReq, nMSHRs))
val meta_read_arb = Module(new Arbiter(new L1MetaReadReq, nMSHRs)) val meta_read_arb = Module(new Arbiter(new L1MetaReadReq, nMSHRs))
val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq, nMSHRs)) val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq, nMSHRs))
val mem_req_arb = Module(new JunctionsCountingArbiter( val mem_req_arb = Module(new LockingArbiter(
new Acquire, new Acquire,
nMSHRs + nIOMSHRs, nMSHRs + nIOMSHRs,
outerDataBeats, outerDataBeats,
@ -948,7 +948,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
metaWriteArb.io.in(0) <> mshrs.io.meta_write metaWriteArb.io.in(0) <> mshrs.io.meta_write
// probes and releases // probes and releases
val releaseArb = Module(new JunctionsCountingArbiter(new Release, 2, outerDataBeats, (r: Release) => r.hasMultibeatData())) val releaseArb = Module(new LockingArbiter(new Release, 2, outerDataBeats, (r: Release) => r.hasMultibeatData()))
io.mem.release <> releaseArb.io.out io.mem.release <> releaseArb.io.out
prober.io.req.valid := io.mem.probe.valid && !lrsc_valid prober.io.req.valid := io.mem.probe.valid && !lrsc_valid