riscv/rocket-chip
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Streamlined uncore for release

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Henry Cook 2014-09-24 18:34:04 -07:00 committed by Yunsup Lee
parent 6c18cd9559
commit 0b5f23a209
3 changed files with 9 additions and 42 deletions
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32
src/main/scala/PublicConfigs.scala
View File

@ -106,43 +106,15 @@ class DefaultConfig extends ChiselConfig {
case TLAtomicOpBits => 4
case NTiles => Knob("NTILES")
case NBanks => Knob("NBANKS")
case NOutstandingMemReqs => 16 //site(NBanks)*(site(NReleaseTransactors)+site(NAcquireTransactors))
case BankIdLSB => 5
case CacheBlockBytes => 64
case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
case UseBackupMemoryPort => true
case BuildDRAMSideLLC => (refill: Int) => {
if(site[Boolean]("USE_DRAMSIDE_LLC")) {
val tag = Mem(Bits(width = 152), 512, seqRead = true)
val data = Mem(Bits(width = 64), 4096, seqRead = true)
Module(new DRAMSideLLC_HasKnownBug(sets=512, ways=8, outstanding=16,
refill_cycles=refill, tagLeaf=tag, dataLeaf=data))
} else {
Module(new DRAMSideLLCNull(site(NReleaseTransactors)+site(NAcquireTransactors), refill))
}
}
case BuildCoherenceMaster => (id: Int) => {
if(site[Boolean]("USE_L2_CACHE")) {
Module(new L2HellaCache(id, "inner", "outer"), { case CacheName => "L2" })
} else {
Module(new L2CoherenceAgent(id, "inner", "outer"), { case CacheName => "L2" })
}
}
case Coherence => {
val dir = () => new FullRepresentation(site(NClients))
val enSharing = site[Boolean]("ENABLE_SHARING")
val enCleanEx = site[Boolean]("ENABLE_CLEAN_EXCLUSIVE")
if(enSharing) {
if(enCleanEx) new MESICoherence(dir)
else new MSICoherence(dir)
} else {
if(enCleanEx) new MEICoherence(dir)
else new MICoherence(dir)
}
}
case "ENABLE_SHARING" => true
case "ENABLE_CLEAN_EXCLUSIVE" => true
case "USE_DRAMSIDE_LLC" => false // DO NOT TURN ON. Read uncore/src/main/scala/llc.scala
case "USE_L2_CACHE" => false
case Coherence => new MSICoherence(() => new NullRepresentation)
}
}
override val knobValues:Any=>Any = {

17
src/main/scala/RocketChip.scala
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@ -9,13 +9,13 @@ import rocket.Util._
case object NTiles extends Field[Int]
case object NBanks extends Field[Int]
case object NOutstandingMemReqs extends Field[Int]
case object BankIdLSB extends Field[Int]
case object CacheBlockBytes extends Field[Int]
case object CacheBlockOffsetBits extends Field[Int]
case object BuildDRAMSideLLC extends Field[(Int) => DRAMSideLLCLike]
case object BuildCoherenceMaster extends Field[(Int) => CoherenceAgent]
case object UseBackupMemoryPort extends Field[Boolean]
case object Coherence extends Field[CoherencePolicyWithUncached]
case object BuildCoherenceMaster extends Field[(Int) => CoherenceAgent]
case object BuildTile extends Field[(Bool)=>Tile]
abstract trait TopLevelParameters extends UsesParameters {
@ -44,7 +44,8 @@ class OuterMemorySystem extends Module with TopLevelParameters {
masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } }
// Create a converter between TileLinkIO and MemIO
val conv = Module(new MemIOUncachedTileLinkIOConverter(2),
val conv = Module(new MemPipeIOUncachedTileLinkIOConverter(
params(NOutstandingMemReqs), refillCycles),
{ case TLId => "outer" })
if(params(NBanks) > 1) {
val arb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(params(NBanks)),
@ -55,18 +56,12 @@ class OuterMemorySystem extends Module with TopLevelParameters {
conv.io.uncached <> masterEndpoints.head.io.outer
}
// Create a DRAM-side LLC
val llc = params(BuildDRAMSideLLC)(refillCycles)
llc.io.cpu.req_cmd <> Queue(conv.io.mem.req_cmd, 2)
llc.io.cpu.req_data <> Queue(conv.io.mem.req_data, refillCycles)
conv.io.mem.resp <> llc.io.cpu.resp
// Create a SerDes for backup memory port
if(params(UseBackupMemoryPort)) {
VLSIUtils.doOuterMemorySystemSerdes(llc.io.mem, io.mem, io.mem_backup,
VLSIUtils.doOuterMemorySystemSerdes(conv.io.mem, io.mem, io.mem_backup,
io.mem_backup_en, htifW)
} else {
io.mem <> llc.io.mem
io.mem <> conv.io.mem
}
}

2
uncore

@ -1 +1 @@
Subproject commit f294eddb44b7455cfaf4d533da1056dc8b88086e
Subproject commit 9924c8d39ad3f16f68855eca9bbbc7705db02433