riscv/rocket-chip
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Add D-mode single-step support

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This commit is contained in:
Andrew Waterman
2016-06-15 16:21:24 -07:00
parent e3816d5fc7
commit 0b4c8e9af7
2 changed files with 19 additions and 11 deletions
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2
rocket/src/main/scala/rocket.scala
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@ -297,7 +297,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
ex_ctrl.csr := id_csr
ex_reg_btb_hit := io.imem.btb_resp.valid
when (io.imem.btb_resp.valid) { ex_reg_btb_resp := io.imem.btb_resp.bits }
ex_reg_flush_pipe := id_ctrl.fence_i || id_csr_flush
ex_reg_flush_pipe := id_ctrl.fence_i || id_csr_flush || csr.io.singleStep
ex_reg_load_use := id_load_use
for (i <- 0 until id_raddr.size) {