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tilelink2 ToAXI4: no arbitration path register needed

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This commit is contained in:
Wesley W. Terpstra 2016-10-12 18:11:09 -07:00
parent 0e897b905f
commit 0aebf9e341
1 changed files with 5 additions and 8 deletions
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13
src/main/scala/uncore/tilelink2/ToAXI4.scala
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@ -221,12 +221,9 @@ class TLToAXI4(idBits: Int, combinational: Boolean = true) extends LazyModule
// Give R higher priority than B // Give R higher priority than B
val r_wins = out.r.valid || r_holds_d val r_wins = out.r.valid || r_holds_d
val in_d = Wire(in.d) out.r.ready := in.d.ready
in.d <> Queue.irrevocable(in_d, entries=1, flow=combinational) out_b.ready := in.d.ready && !r_wins
in.d.valid := Mux(r_wins, out.r.valid, out_b.valid)
out.r.ready := in_d.ready
out_b.ready := in_d.ready && !r_wins
in_d.valid := Mux(r_wins, out.r.valid, out_b.valid)
val r_error = out.r.bits.resp =/= AXI4Parameters.RESP_OKAY val r_error = out.r.bits.resp =/= AXI4Parameters.RESP_OKAY
val b_error = out_b.bits.resp =/= AXI4Parameters.RESP_OKAY val b_error = out_b.bits.resp =/= AXI4Parameters.RESP_OKAY
@ -234,8 +231,8 @@ class TLToAXI4(idBits: Int, combinational: Boolean = true) extends LazyModule
val r_d = edgeIn.AccessAck(r_addr_lo, r_sink, r_source, r_size, UInt(0), r_error) val r_d = edgeIn.AccessAck(r_addr_lo, r_sink, r_source, r_size, UInt(0), r_error)
val b_d = edgeIn.AccessAck(b_addr_lo, b_sink, b_source, b_size, b_error) val b_d = edgeIn.AccessAck(b_addr_lo, b_sink, b_source, b_size, b_error)
in_d.bits := Mux(r_wins, r_d, b_d) in.d.bits := Mux(r_wins, r_d, b_d)
in_d.bits.data := out.r.bits.data // avoid a costly Mux in.d.bits.data := out.r.bits.data // avoid a costly Mux
// Tie off unused channels // Tie off unused channels
in.b.valid := Bool(false) in.b.valid := Bool(false)