Allow additional internal MMIO devices to be created without changing BaseConfig

junctions/src/main/scala/addrmap.scala

@@ -125,6 +125,7 @@ class AddrMap(entriesIn: Seq[AddrMapEntry], val start: BigInt = BigInt(0)) exten
   }
 
   def apply(name: String): MemRegion = mapping(name)
+  def contains(name: String): Boolean = mapping.contains(name)
   def port(name: String): Int = slavePorts(name)
   def subMap(name: String): AddrMap = mapping(name).asInstanceOf[AddrMap]
   def isInRegion(name: String, addr: UInt): Bool = mapping(name).containsAddress(addr)

src/main/scala/Configs.scala

@@ -34,6 +34,7 @@ class BaseConfig extends Config (
       entries += AddrMapEntry("bootrom", MemSize(4096, MemAttr(AddrMapProt.RX)))
       entries += AddrMapEntry("plic", MemRange(0x40000000, 0x4000000, MemAttr(AddrMapProt.RW)))
       entries += AddrMapEntry("prci", MemSize(0x4000000, MemAttr(AddrMapProt.RW)))
+      entries ++= site(ExtraMMIODevices).entries
       new AddrMap(entries)
     }
     lazy val globalAddrMap = {
@@ -94,6 +95,13 @@ class BaseConfig extends Config (
         res append  "    };\n"
         res append  "  };\n"
       }
+      for (device <- site(ExtraMMIODevices).entries) {
+        val deviceEntry = addrMap("io:int:" + device.name)
+        res append s"  ${device.name} {\n"
+        res append s"    addr 0x${deviceEntry.start.toString(16)};\n"
+        res append s"    size 0x${deviceEntry.size.toString(16)};\n"
+        res append s"  };\n"
+      }
       res append  "};\n"
       res append '\u0000'
       res.toString.getBytes
@@ -223,6 +231,7 @@ class BaseConfig extends Config (
       }
       case NExtInterrupts => 2
       case AsyncMMIOChannels => false
+      case ExtraMMIODevices => AddrMap()
       case ExtMMIOPorts => AddrMap()
 /*
         AddrMap(
@@ -585,14 +594,6 @@ class MIF128BitConfig extends Config(
 class MIF32BitConfig extends Config(
   new WithMIFDataBits(32) ++ new BaseConfig)
 
-class WithStreamLoopback extends Config(
-  (pname, site, here) => pname match {
-    case UseStreamLoopback => true
-    case StreamLoopbackSize => 128
-    case StreamLoopbackWidth => 64
-    case _ => throw new CDEMatchError
-  })
-
 class SmallL2Config extends Config(
   new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++
   new WithL2Capacity(256) ++ new DefaultL2Config)
@@ -613,3 +614,9 @@ class DualCoreConfig extends Config(
 class TinyConfig extends Config(
   new WithRV32 ++ new WithSmallCores ++
   new WithStatelessBridge ++ new BaseConfig)
+
+class WithTestRAM extends Config(
+  (pname, site, here) => pname match {
+    case ExtraMMIODevices => AddrMap(
+      AddrMapEntry("testram", MemSize(0x1000, MemAttr(AddrMapProt.RW))))
+  })

src/main/scala/RocketChip.scala

@@ -56,10 +56,7 @@ case object PLICKey extends Field[PLICConfig]
 /** Number of clock cycles per RTC tick */
 case object RTCPeriod extends Field[Int]
 case object AsyncDebugBus extends Field[Boolean]
-
+case object ExtraMMIODevices extends Field[AddrMap]
-case object UseStreamLoopback extends Field[Boolean]
-case object StreamLoopbackSize extends Field[Int]
-case object StreamLoopbackWidth extends Field[Int]
 
 /** Utility trait for quick access to some relevant parameters */
 trait HasTopLevelParameters {
@@ -254,7 +251,7 @@ class Uncore(implicit val p: Parameters) extends Module
     val mmio_tl_start  = mmio_ahb_end
     val mmio_tl_end    = mmio_tl_start  + p(NExtMMIOTLChannels)
     require (mmio_tl_end == ports.size)
-    
+
     for (i <- 0 until ports.size) {
       if (mmio_axi_start <= i && i < mmio_axi_end) {
         TopUtils.connectTilelinkNasti(io.mmio_axi(i-mmio_axi_start), ports(i))
@@ -328,7 +325,12 @@ class Uncore(implicit val p: Parameters) extends Module
     val bootROM = Module(new ROMSlave(makeBootROM()))
     bootROM.io <> mmioNetwork.port("int:bootrom")
 
-    // The memory map presently has only one external I/O region
+    if (ioAddrMap.contains("int:testram")) {
+      val ramSize = ioAddrMap("int:testram").size.intValue
+      val testram = Module(new TileLinkTestRAM(ramSize))
+      testram.io <> mmioNetwork.port("int:testram")
+    }
+
     val ext = p(ExtMMIOPorts).entries.map(port => TileLinkWidthAdapter(mmioNetwork.port(port.name), "MMIO_Outermost"))
     connectExternalMMIO(ext)(outermostMMIOParams)
   }

src/main/scala/TestConfigs.scala

@@ -69,7 +69,7 @@ class WithComparator extends Config(
     case BuildGroundTest =>
       (p: Parameters) => Module(new ComparatorCore()(p))
     case ComparatorKey => ComparatorParameters(
-      targets    = Seq(0L, 0x100L).map(site(GlobalAddrMap)("mem").start.longValue + _),
+      targets    = Seq("mem", "io:int:testram").map(name => site(GlobalAddrMap)(name).start.longValue),
       width      = 8,
       operations = 1000,
       atomics    = site(UseAtomics),
@@ -224,7 +224,8 @@ class WithTraceGen extends Config(
 
 class GroundTestConfig extends Config(new WithGroundTest ++ new BaseConfig)
 
-class ComparatorConfig extends Config(new WithComparator ++ new GroundTestConfig)
+class ComparatorConfig extends Config(
+  new WithTestRAM ++ new WithComparator ++ new GroundTestConfig)
 class ComparatorL2Config extends Config(
   new WithAtomics ++ new WithPrefetches ++
   new WithL2Cache ++ new ComparatorConfig)

uncore/src/main/scala/devices/Bram.scala

@@ -130,6 +130,10 @@ class TileLinkTestRAM(depth: Int)(implicit val p: Parameters) extends Module
     } .otherwise { responding := Bool(false) }
   }
 
+  val old_data = ram(acq_addr)
+  val new_data = acq.data
+  val r_old_data = RegEnable(old_data, io.acquire.fire())
+
   io.acquire.ready := !responding
   io.grant.valid := responding
   io.grant.bits := Grant(
@@ -138,13 +142,10 @@ class TileLinkTestRAM(depth: Int)(implicit val p: Parameters) extends Module
     client_xact_id = r_acq.client_xact_id,
     manager_xact_id = UInt(0),
     addr_beat = r_acq.addr_beat,
-    data = ram(r_acq_addr))
+    data = Mux(r_acq.isAtomic(), r_old_data, ram(r_acq_addr)))
-
-  val old_data = ram(acq_addr)
-  val new_data = acq.data
 
   val amo_shift_bits = acq.amo_shift_bytes() << UInt(3)
-  val amoalu = Module(new AMOALU)
+  val amoalu = Module(new AMOALU(rhsIsAligned = true))
   amoalu.io.addr := Cat(acq.addr_block, acq.addr_beat, acq.addr_byte())
   amoalu.io.cmd := acq.op_code()
   amoalu.io.typ := acq.op_size()