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Allow additional internal MMIO devices to be created without changing BaseConfig

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This commit is contained in:
Howard Mao
2016-08-03 16:33:30 -07:00
parent cc0f8962fb
commit 0a85e92652
5 changed files with 33 additions and 21 deletions
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11
uncore/src/main/scala/devices/Bram.scala
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@ -130,6 +130,10 @@ class TileLinkTestRAM(depth: Int)(implicit val p: Parameters) extends Module
} .otherwise { responding := Bool(false) }
}
val old_data = ram(acq_addr)
val new_data = acq.data
val r_old_data = RegEnable(old_data, io.acquire.fire())
io.acquire.ready := !responding
io.grant.valid := responding
io.grant.bits := Grant(
@ -138,13 +142,10 @@ class TileLinkTestRAM(depth: Int)(implicit val p: Parameters) extends Module
client_xact_id = r_acq.client_xact_id,
manager_xact_id = UInt(0),
addr_beat = r_acq.addr_beat,
data = ram(r_acq_addr))
val old_data = ram(acq_addr)
val new_data = acq.data
data = Mux(r_acq.isAtomic(), r_old_data, ram(r_acq_addr)))
val amo_shift_bits = acq.amo_shift_bytes() << UInt(3)
val amoalu = Module(new AMOALU)
val amoalu = Module(new AMOALU(rhsIsAligned = true))
amoalu.io.addr := Cat(acq.addr_block, acq.addr_beat, acq.addr_byte())
amoalu.io.cmd := acq.op_code()
amoalu.io.typ := acq.op_size()