diff --git a/csrc/emulator.cc b/csrc/emulator.cc
index db914704..af6e0ac0 100644
--- a/csrc/emulator.cc
+++ b/csrc/emulator.cc
@@ -65,7 +65,7 @@ int main(int argc, char** argv)
   srand48(random_seed);
 
   Verilated::randReset(2);
-  VTestHarness *tile = new VTestHarness;
+  MODEL *tile = new MODEL;
 
 #if VM_TRACE
   Verilated::traceEverOn(true); // Verilator must compute traced signals
diff --git a/emulator/Makefrag-verilator b/emulator/Makefrag-verilator
index 2cf13f33..2e4435cb 100644
--- a/emulator/Makefrag-verilator
+++ b/emulator/Makefrag-verilator
@@ -54,7 +54,7 @@ VERILATOR_FLAGS := --top-module $(MODEL) \
   +define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
 	-Wno-STMTDLY --x-assign unique \
   -I$(base_dir)/vsrc \
-  -O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/csrc/verilator.h"
+  -O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/csrc/verilator.h -DMODEL=V$(MODEL)"
 cppfiles = $(addprefix $(base_dir)/csrc/, $(addsuffix .cc, $(CXXSRCS)))
 headers = $(wildcard $(base_dir)/csrc/*.h)
 
diff --git a/regression/Makefile b/regression/Makefile
index ca210738..7d222c4f 100644
--- a/regression/Makefile
+++ b/regression/Makefile
@@ -39,11 +39,13 @@ $(error Set SUITE to the regression suite you want to run)
 endif
 
 ifeq ($(SUITE),RocketSuite)
+MODEL=TestHarness
 PROJECT=rocketchip
 CONFIGS=DefaultConfig DefaultL2Config DefaultBufferlessConfig TinyConfig
 endif
 
 ifeq ($(SUITE),GroundtestSuite)
+MODEL=TestHarness
 PROJECT=rocketchip
 CONFIGS=MemtestConfig MemtestBufferlessConfig MemtestStatelessConfig FancyMemtestConfig \
 	BroadcastRegressionTestConfig BufferlessRegressionTestConfig CacheRegressionTestConfig \
@@ -51,7 +53,8 @@ CONFIGS=MemtestConfig MemtestBufferlessConfig MemtestStatelessConfig FancyMemtes
 endif
 
 ifeq ($(SUITE),UnittestSuite)
-PROJECT=rocketchip.utest
+MODEL=UnitTestHarness
+PROJECT=rocketchip
 CONFIGS=UnitTestConfig
 endif
 
@@ -123,65 +126,65 @@ $(RISCV)/install.stamp:
 # Builds the various simulators
 stamps/%/emulator-verilog.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
 	mkdir -p $(dir $@)
-	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) verilog
+	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) verilog
 	date > $@
 
 stamps/%/emulator-ndebug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
 	mkdir -p $(dir $@)
-	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV))
+	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV))
 	date > $@
 
 stamps/%/emulator-debug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
 	mkdir -p $(dir $@)
-	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) debug
+	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) debug
 	date > $@
 
 stamps/%/vsim-verilog.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
 	mkdir -p $(dir $@)
-	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) verilog
+	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) verilog
 	date > $@
 
 stamps/%/vsim-ndebug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
 	mkdir -p $(dir $@)
-	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV))
+	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV))
 	date > $@
 
 stamps/%/vsim-debug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
 	mkdir -p $(dir $@)
-	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) debug
+	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) debug
 	date > $@
 
 # Runs tests on one of the simulators
 stamps/%/emulator-asm-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
 	mkdir -p $(dir $@)
-	$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-asm-tests-fast
+	$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) run-asm-tests-fast
 	date > $@
 
 stamps/%/emulator-bmark-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
 	mkdir -p $(dir $@)
-	$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-bmark-tests-fast
+	$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) run-bmark-tests-fast
 	date > $@
 
 stamps/%/emulator-regression-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
 	mkdir -p $(dir $@)
-	$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) clean-run-output
-	$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-regression-tests-fast
+	$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) clean-run-output
+	$(MAKE) -C $(abspath $(TOP))/emulator PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) run-regression-tests-fast
 	date > $@
 
 stamps/%/vsim-asm-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
 	mkdir -p $(dir $@)
-	$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-asm-tests-fast
+	$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) run-asm-tests-fast
 	date > $@
 
 stamps/%/vsim-bmark-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
 	mkdir -p $(dir $@)
-	$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-bmark-tests-fast
+	$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) run-bmark-tests-fast
 	date > $@
 
 stamps/%/vsim-regression-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
 	mkdir -p $(dir $@)
-	$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) clean-run-output
-	$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) CONFIG=$* RISCV=$(abspath $(RISCV)) run-regression-tests-fast
+	$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) clean-run-output
+	$(MAKE) -C $(abspath $(TOP))/vsim PROJECT=$(PROJECT) MODEL=$(MODEL) CONFIG=$* RISCV=$(abspath $(RISCV)) run-regression-tests-fast
 	date > $@
 
 # The torture tests run subtly differently on the different targets, so they
diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala
index 2594cdf6..8d8d87ad 100644
--- a/src/main/scala/coreplex/Configs.scala
+++ b/src/main/scala/coreplex/Configs.scala
@@ -189,7 +189,7 @@ class BaseCoreplexConfig extends Config (
       case TLKey("MMIO_Outermost") => site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))
 
       case BootROMFile => "./bootrom/bootrom.img"
-      case NTiles => Knob("NTILES")
+      case NTiles => 1
       case NBanksPerMemoryChannel => Knob("NBANKS_PER_MEM_CHANNEL")
       case BankIdLSB => 0
       case CacheBlockBytes => Dump("CACHE_BLOCK_BYTES", 64)
@@ -224,7 +224,6 @@ class BaseCoreplexConfig extends Config (
       case _ => throw new CDEMatchError
   }},
   knobValues = {
-    case "NTILES" => 1
     case "NBANKS_PER_MEM_CHANNEL" => 1
     case "L1D_MSHRS" => 2
     case "L1D_SETS" => 64
@@ -236,7 +235,9 @@ class BaseCoreplexConfig extends Config (
 )
 
 class WithNCores(n: Int) extends Config(
-  knobValues = { case"NTILES" => n; case _ => throw new CDEMatchError })
+  (pname,site,here) => pname match {
+    case NTiles => n
+  })
 
 class WithNBanksPerMemChannel(n: Int) extends Config(
   knobValues = {
diff --git a/src/main/scala/coreplex/Coreplex.scala b/src/main/scala/coreplex/Coreplex.scala
index 2ccad311..2da93f9f 100644
--- a/src/main/scala/coreplex/Coreplex.scala
+++ b/src/main/scala/coreplex/Coreplex.scala
@@ -11,8 +11,6 @@ import uncore.util._
 import uncore.converters._
 import rocket._
 import rocket.Util._
-import java.nio.{ByteBuffer,ByteOrder}
-import java.nio.file.{Files, Paths}
 
 /** Number of memory channels */
 case object NMemoryChannels extends Field[Int]
@@ -34,7 +32,6 @@ trait HasCoreplexParameters {
   lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
   lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" })
   lazy val outermostMMIOParams = p.alterPartial({ case TLId => "MMIO_Outermost" })
-  lazy val configString = p(rocketchip.ConfigString).get
   lazy val globalAddrMap = p(rocketchip.GlobalAddrMap).get
 }
 
@@ -120,38 +117,16 @@ class DefaultCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp,
     val backendBuffering = TileLinkDepths(0,0,0,0,0)
     for ((bank, icPort) <- managerEndpoints zip mem_ic.io.in) {
       val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
-      unwrap.io.in <> ClientTileLinkEnqueuer(bank.outerTL, backendBuffering)(outerTLParams)
+      unwrap.io.in <> TileLinkEnqueuer(bank.outerTL, backendBuffering)(outerTLParams)
       TileLinkWidthAdapter(icPort, unwrap.io.out)
     }
 
     io.master.mem <> mem_ic.io.out
 
-    buildMMIONetwork(ClientUncachedTileLinkEnqueuer(mmioManager.io.outer, 1))(
+    buildMMIONetwork(TileLinkEnqueuer(mmioManager.io.outer, 1))(
         p.alterPartial({case TLId => "L2toMMIO"}))
   }
 
-  def makeBootROM()(implicit p: Parameters) = {
-    val romdata = Files.readAllBytes(Paths.get(p(BootROMFile)))
-    val rom = ByteBuffer.wrap(romdata)
-
-    rom.order(ByteOrder.LITTLE_ENDIAN)
-
-    // for now, have the reset vector jump straight to memory
-    val memBase = (
-      if (globalAddrMap contains "mem") globalAddrMap("mem")
-      else globalAddrMap("io:int:dmem0")
-    ).start
-    val resetToMemDist = memBase - p(ResetVector)
-    require(resetToMemDist == (resetToMemDist.toInt >> 12 << 12))
-    val configStringAddr = p(ResetVector).toInt + rom.capacity
-
-    require(rom.getInt(12) == 0,
-      "Config string address position should not be occupied by code")
-    rom.putInt(12, configStringAddr)
-    rom.array() ++ (configString.getBytes.toSeq)
-  }
-
-
   def buildMMIONetwork(mmio: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
     val ioAddrMap = globalAddrMap.subMap("io")
 
@@ -182,10 +157,7 @@ class DefaultCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp,
 
     val tileSlavePorts = (0 until tc.nTiles) map (i => s"int:dmem$i") filter (ioAddrMap contains _)
     for ((t, m) <- (tileList.map(_.io.slave).flatten) zip (tileSlavePorts map (mmioNetwork port _)))
-      t <> ClientUncachedTileLinkEnqueuer(m, 1)
-
-    val bootROM = Module(new ROMSlave(makeBootROM()))
-    bootROM.io <> mmioNetwork.port("int:bootrom")
+      t <> TileLinkEnqueuer(m, 1)
 
     io.master.mmio.foreach { _ <> mmioNetwork.port("ext") }
   }
diff --git a/src/main/scala/groundtest/Regression.scala b/src/main/scala/groundtest/Regression.scala
index ff8010a6..ef9eb576 100644
--- a/src/main/scala/groundtest/Regression.scala
+++ b/src/main/scala/groundtest/Regression.scala
@@ -72,7 +72,7 @@ class IOGetAfterPutBlockRegression(implicit p: Parameters) extends Regression()(
   io.mem.grant.ready := Bool(true)
 
   io.cache.req.valid := !get_sent && started
-  io.cache.req.bits.addr := UInt(addrMap("io:int:bootrom").start)
+  io.cache.req.bits.addr := UInt(addrMap("io:ext:bootrom").start)
   io.cache.req.bits.typ := UInt(log2Ceil(32 / 8))
   io.cache.req.bits.cmd := M_XRD
   io.cache.req.bits.tag := UInt(0)
diff --git a/src/main/scala/junctions/nasti.scala b/src/main/scala/junctions/nasti.scala
index 48cd4fb5..ab580523 100644
--- a/src/main/scala/junctions/nasti.scala
+++ b/src/main/scala/junctions/nasti.scala
@@ -135,6 +135,17 @@ object NastiConstants {
   val RESP_EXOKAY = UInt("b01")
   val RESP_SLVERR = UInt("b10")
   val RESP_DECERR = UInt("b11")
+
+  val CACHE_DEVICE_NOBUF = UInt("b0000")
+  val CACHE_DEVICE_BUF   = UInt("b0001")
+  val CACHE_NORMAL_NOCACHE_NOBUF = UInt("b0010")
+  val CACHE_NORMAL_NOCACHE_BUF   = UInt("b0011")
+
+  def AXPROT(instruction: Bool, nonsecure: Bool, privileged: Bool): UInt =
+    Cat(instruction, nonsecure, privileged)
+
+  def AXPROT(instruction: Boolean, nonsecure: Boolean, privileged: Boolean): UInt =
+    AXPROT(Bool(instruction), Bool(nonsecure), Bool(privileged))
 }
 
 import NastiConstants._
@@ -150,8 +161,8 @@ object NastiWriteAddressChannel {
     aw.size := size
     aw.burst := burst
     aw.lock := Bool(false)
-    aw.cache := UInt("b0000")
-    aw.prot := UInt("b000")
+    aw.cache := CACHE_DEVICE_NOBUF
+    aw.prot := AXPROT(false, false, false)
     aw.qos := UInt("b0000")
     aw.region := UInt("b0000")
     aw.user := UInt(0)
@@ -170,8 +181,8 @@ object NastiReadAddressChannel {
     ar.size := size
     ar.burst := burst
     ar.lock := Bool(false)
-    ar.cache := UInt(0)
-    ar.prot := UInt(0)
+    ar.cache := CACHE_DEVICE_NOBUF
+    ar.prot := AXPROT(false, false, false)
     ar.qos := UInt(0)
     ar.region := UInt(0)
     ar.user := UInt(0)
@@ -255,7 +266,7 @@ class MemIONastiIOConverter(cacheBlockOffsetBits: Int)(implicit p: Parameters) e
 
   io.nasti.b.valid := id_q.io.deq.valid && b_ok
   io.nasti.b.bits.id := id_q.io.deq.bits
-  io.nasti.b.bits.resp := UInt(0)
+  io.nasti.b.bits.resp := RESP_OKAY
 
   io.nasti.w.ready := io.mem.req_data.ready
   io.mem.req_data.valid := io.nasti.w.valid
@@ -266,7 +277,7 @@ class MemIONastiIOConverter(cacheBlockOffsetBits: Int)(implicit p: Parameters) e
   io.nasti.r.bits.data := io.mem.resp.bits.data
   io.nasti.r.bits.last := mif_wrap_out
   io.nasti.r.bits.id := io.mem.resp.bits.tag
-  io.nasti.r.bits.resp := UInt(0)
+  io.nasti.r.bits.resp := RESP_OKAY
   io.mem.resp.ready := io.nasti.r.ready
 }
 
@@ -389,7 +400,7 @@ class NastiErrorSlave(implicit p: Parameters) extends NastiModule {
   io.aw.ready := b_queue.io.enq.ready && !draining
   io.b.valid := b_queue.io.deq.valid && !draining
   io.b.bits.id := b_queue.io.deq.bits
-  io.b.bits.resp := Bits("b11")
+  io.b.bits.resp := RESP_DECERR
   b_queue.io.deq.ready := io.b.ready && !draining
 }
 
diff --git a/src/main/scala/junctions/smi.scala b/src/main/scala/junctions/smi.scala
deleted file mode 100644
index 4a8559a8..00000000
--- a/src/main/scala/junctions/smi.scala
+++ /dev/null
@@ -1,281 +0,0 @@
-package junctions
-
-import Chisel._
-import cde.Parameters
-
-class SmiReq(val dataWidth: Int, val addrWidth: Int) extends Bundle {
-  val rw = Bool()
-  val addr = UInt(width = addrWidth)
-  val data = Bits(width = dataWidth)
-
-  override def cloneType =
-    new SmiReq(dataWidth, addrWidth).asInstanceOf[this.type]
-}
-
-/** Simple Memory Interface IO. Used to communicate with PCR and SCR
- *  @param dataWidth the width in bits of the data field
- *  @param addrWidth the width in bits of the addr field */
-class SmiIO(val dataWidth: Int, val addrWidth: Int) extends Bundle {
-  val req = Decoupled(new SmiReq(dataWidth, addrWidth))
-  val resp = Decoupled(Bits(width = dataWidth)).flip
-
-  override def cloneType =
-    new SmiIO(dataWidth, addrWidth).asInstanceOf[this.type]
-}
-
-abstract class SmiPeripheral extends Module {
-  val dataWidth: Int
-  val addrWidth: Int
-
-  lazy val io = new SmiIO(dataWidth, addrWidth).flip
-}
-
-/** A simple sequential memory accessed through Smi */
-class SmiMem(val dataWidth: Int, val memDepth: Int) extends SmiPeripheral {
-  // override
-  val addrWidth = log2Up(memDepth)
-
-  val mem = SeqMem(memDepth, Bits(width = dataWidth))
-
-  val ren = io.req.fire() && !io.req.bits.rw
-  val wen = io.req.fire() && io.req.bits.rw
-
-  when (wen) { mem.write(io.req.bits.addr, io.req.bits.data) }
-
-  val resp_valid = Reg(init = Bool(false))
-
-  when (io.resp.fire()) { resp_valid := Bool(false) }
-  when (io.req.fire())  { resp_valid := Bool(true) }
-
-  io.resp.valid := resp_valid
-  io.resp.bits := mem.read(io.req.bits.addr, ren)
-  io.req.ready := !resp_valid
-}
-
-/** Arbitrate among several Smi clients
- *  @param n the number of clients
- *  @param dataWidth Smi data width
- *  @param addrWidth Smi address width */
-class SmiArbiter(val n: Int, val dataWidth: Int, val addrWidth: Int)
-    extends Module {
-  val io = new Bundle {
-    val in = Vec(n, new SmiIO(dataWidth, addrWidth)).flip
-    val out = new SmiIO(dataWidth, addrWidth)
-  }
-
-  val wait_resp = Reg(init = Bool(false))
-  val choice = Reg(UInt(width = log2Up(n)))
-
-  val req_arb = Module(new RRArbiter(new SmiReq(dataWidth, addrWidth), n))
-  req_arb.io.in <> io.in.map(_.req)
-  req_arb.io.out.ready := io.out.req.ready && !wait_resp
-
-  io.out.req.bits := req_arb.io.out.bits
-  io.out.req.valid := req_arb.io.out.valid && !wait_resp
-
-  when (io.out.req.fire()) {
-    choice := req_arb.io.chosen
-    wait_resp := Bool(true)
-  }
-
-  when (io.out.resp.fire()) { wait_resp := Bool(false) }
-
-  for ((resp, i) <- io.in.map(_.resp).zipWithIndex) {
-    resp.bits := io.out.resp.bits
-    resp.valid := io.out.resp.valid && choice === UInt(i)
-  }
-
-  io.out.resp.ready := io.in(choice).resp.ready
-}
-
-class SmiIONastiReadIOConverter(val dataWidth: Int, val addrWidth: Int)
-                               (implicit p: Parameters) extends NastiModule()(p) {
-  val io = new Bundle {
-    val nasti = new NastiReadIO().flip
-    val smi = new SmiIO(dataWidth, addrWidth)
-  }
-
-  private val maxWordsPerBeat = nastiXDataBits / dataWidth
-  private val wordCountBits = log2Up(maxWordsPerBeat)
-  private val byteOffBits = log2Up(dataWidth / 8)
-  private val addrOffBits = addrWidth + byteOffBits
-
-  private def calcWordCount(size: UInt): UInt =
-    (UInt(1) << (size - UInt(byteOffBits))) - UInt(1)
-
-  val (s_idle :: s_read :: s_resp :: Nil) = Enum(Bits(), 3)
-  val state = Reg(init = s_idle)
-
-  val nWords = Reg(UInt(width = wordCountBits))
-  val nBeats = Reg(UInt(width = nastiXLenBits))
-  val addr = Reg(UInt(width = addrWidth))
-  val id = Reg(UInt(width = nastiRIdBits))
-
-  val byteOff = Reg(UInt(width = byteOffBits))
-  val recvInd = Reg(init = UInt(0, wordCountBits))
-  val sendDone = Reg(init = Bool(false))
-
-  val buffer = Reg(init = Vec.fill(maxWordsPerBeat) { Bits(0, dataWidth) })
-
-  io.nasti.ar.ready := (state === s_idle)
-
-  io.smi.req.valid := (state === s_read) && !sendDone
-  io.smi.req.bits.rw := Bool(false)
-  io.smi.req.bits.addr := addr
-
-  io.smi.resp.ready := (state === s_read)
-
-  io.nasti.r.valid := (state === s_resp)
-  io.nasti.r.bits := NastiReadDataChannel(
-    id = id,
-    data = buffer.asUInt,
-    last = (nBeats === UInt(0)))
-
-  when (io.nasti.ar.fire()) {
-    when (io.nasti.ar.bits.size < UInt(byteOffBits)) {
-      nWords := UInt(0)
-    } .otherwise {
-      nWords := calcWordCount(io.nasti.ar.bits.size)
-    }
-    nBeats := io.nasti.ar.bits.len
-    addr := io.nasti.ar.bits.addr(addrOffBits - 1, byteOffBits)
-    if (maxWordsPerBeat > 1)
-      recvInd := io.nasti.ar.bits.addr(wordCountBits + byteOffBits - 1, byteOffBits)
-    else
-      recvInd := UInt(0)
-    id := io.nasti.ar.bits.id
-    state := s_read
-  }
-
-  when (io.smi.req.fire()) {
-    addr := addr + UInt(1)
-    sendDone := (nWords === UInt(0))
-  }
-
-  when (io.smi.resp.fire()) {
-    recvInd := recvInd + UInt(1)
-    nWords := nWords - UInt(1)
-    buffer(recvInd) := io.smi.resp.bits
-    when (nWords === UInt(0)) { state := s_resp }
-  }
-
-  when (io.nasti.r.fire()) {
-    recvInd := UInt(0)
-    sendDone := Bool(false)
-    // clear all the registers in the buffer
-    buffer.foreach(_ := Bits(0))
-    nBeats := nBeats - UInt(1)
-    state := Mux(io.nasti.r.bits.last, s_idle, s_read)
-  }
-}
-
-class SmiIONastiWriteIOConverter(val dataWidth: Int, val addrWidth: Int)
-                                (implicit p: Parameters) extends NastiModule()(p) {
-  val io = new Bundle {
-    val nasti = new NastiWriteIO().flip
-    val smi = new SmiIO(dataWidth, addrWidth)
-  }
-
-  private val dataBytes = dataWidth / 8
-  private val maxWordsPerBeat = nastiXDataBits / dataWidth
-  private val byteOffBits = log2Floor(dataBytes)
-  private val addrOffBits = addrWidth + byteOffBits
-  private val nastiByteOffBits = log2Ceil(nastiXDataBits / 8)
-
-  assert(!io.nasti.aw.valid || io.nasti.aw.bits.size >= UInt(byteOffBits),
-    "Nasti size must be >= Smi size")
-
-  val id = Reg(UInt(width = nastiWIdBits))
-  val addr = Reg(UInt(width = addrWidth))
-  val offset = Reg(UInt(width = nastiByteOffBits))
-
-  def makeStrobe(offset: UInt, size: UInt, strb: UInt) = {
-    val sizemask = (UInt(1) << (UInt(1) << size)) - UInt(1)
-    val bytemask = strb & (sizemask << offset)
-    Vec.tabulate(maxWordsPerBeat){i => bytemask(dataBytes * i)}.asUInt
-  }
-
-  val size = Reg(UInt(width = nastiXSizeBits))
-  val strb = Reg(UInt(width = maxWordsPerBeat))
-  val data = Reg(UInt(width = nastiXDataBits))
-  val last = Reg(Bool())
-
-  val s_idle :: s_data :: s_send :: s_ack :: s_resp :: Nil = Enum(Bits(), 5)
-  val state = Reg(init = s_idle)
-
-  io.nasti.aw.ready := (state === s_idle)
-  io.nasti.w.ready := (state === s_data)
-  io.smi.req.valid := (state === s_send) && strb(0)
-  io.smi.req.bits.rw := Bool(true)
-  io.smi.req.bits.addr := addr
-  io.smi.req.bits.data := data(dataWidth - 1, 0)
-  io.smi.resp.ready := (state === s_ack)
-  io.nasti.b.valid := (state === s_resp)
-  io.nasti.b.bits := NastiWriteResponseChannel(id)
-
-  val jump = if (maxWordsPerBeat > 1)
-    PriorityMux(strb(maxWordsPerBeat - 1, 1),
-      (1 until maxWordsPerBeat).map(UInt(_)))
-    else UInt(1)
-
-  when (io.nasti.aw.fire()) {
-    if (dataWidth == nastiXDataBits) {
-      addr := io.nasti.aw.bits.addr(addrOffBits - 1, byteOffBits)
-    } else {
-      addr := Cat(io.nasti.aw.bits.addr(addrOffBits - 1, nastiByteOffBits),
-                  UInt(0, nastiByteOffBits - byteOffBits))
-    }
-    offset := io.nasti.aw.bits.addr(nastiByteOffBits - 1, 0)
-    id := io.nasti.aw.bits.id
-    size := io.nasti.aw.bits.size
-    last := Bool(false)
-    state := s_data
-  }
-
-  when (io.nasti.w.fire()) {
-    last := io.nasti.w.bits.last
-    strb := makeStrobe(offset, size, io.nasti.w.bits.strb)
-    data := io.nasti.w.bits.data
-    state := s_send
-  }
-
-  when (state === s_send) {
-    when (io.smi.req.ready || !strb(0)) {
-      strb := strb >> jump
-      data := data >> Cat(jump, UInt(0, log2Up(dataWidth)))
-      addr := addr + jump
-      when (strb(0)) { state := s_ack }
-    }
-  }
-
-  when (io.smi.resp.fire()) {
-    state := Mux(strb === UInt(0),
-              Mux(last, s_resp, s_data), s_send)
-  }
-
-  when (io.nasti.b.fire()) { state := s_idle }
-}
-
-/** Convert Nasti protocol to Smi protocol */
-class SmiIONastiIOConverter(val dataWidth: Int, val addrWidth: Int)
-                           (implicit p: Parameters) extends NastiModule()(p) {
-  val io = new Bundle {
-    val nasti = (new NastiIO).flip
-    val smi = new SmiIO(dataWidth, addrWidth)
-  }
-
-  require(isPow2(dataWidth), "SMI data width must be power of 2")
-  require(dataWidth <= nastiXDataBits,
-    "SMI data width must be less than or equal to NASTI data width")
-
-  val reader = Module(new SmiIONastiReadIOConverter(dataWidth, addrWidth))
-  reader.io.nasti <> io.nasti
-
-  val writer = Module(new SmiIONastiWriteIOConverter(dataWidth, addrWidth))
-  writer.io.nasti <> io.nasti
-
-  val arb = Module(new SmiArbiter(2, dataWidth, addrWidth))
-  arb.io.in(0) <> reader.io.smi
-  arb.io.in(1) <> writer.io.smi
-  io.smi <> arb.io.out
-}
diff --git a/src/main/scala/junctions/stream.scala b/src/main/scala/junctions/stream.scala
index a9e01af8..24f9ad58 100644
--- a/src/main/scala/junctions/stream.scala
+++ b/src/main/scala/junctions/stream.scala
@@ -45,7 +45,7 @@ class NastiIOStreamIOConverter(w: Int)(implicit p: Parameters) extends Module {
   io.nasti.ar.ready := !reading
   io.nasti.r.valid := reading && io.stream.in.valid
   io.nasti.r.bits := io.stream.in.bits
-  io.nasti.r.bits.resp := UInt(0)
+  io.nasti.r.bits.resp := RESP_OKAY
   io.nasti.r.bits.id := read_id
   io.stream.in.ready := reading && io.nasti.r.ready
 
@@ -72,7 +72,7 @@ class NastiIOStreamIOConverter(w: Int)(implicit p: Parameters) extends Module {
   io.stream.out.valid := writing && io.nasti.w.valid
   io.stream.out.bits := io.nasti.w.bits
   io.nasti.b.valid := write_resp
-  io.nasti.b.bits.resp := UInt(0)
+  io.nasti.b.bits.resp := RESP_OKAY
   io.nasti.b.bits.id := write_id
 
   when (io.nasti.aw.fire()) {
diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala
index cdf6e5fd..5fd15e97 100644
--- a/src/main/scala/rocketchip/Periphery.scala
+++ b/src/main/scala/rocketchip/Periphery.scala
@@ -5,6 +5,7 @@ package rocketchip
 import Chisel._
 import cde.{Parameters, Field}
 import junctions._
+import junctions.NastiConstants._
 import uncore.tilelink._
 import uncore.tilelink2.{LazyModule, LazyModuleImp}
 import uncore.converters._
@@ -165,8 +166,8 @@ trait PeripheryMasterMemModule extends HasPeripheryParameters {
   // Abuse the fact that zip takes the shorter of the two lists
   ((io.mem_axi zip coreplex.io.master.mem) zipWithIndex) foreach { case ((axi, mem), idx) =>
     val axi_sync = PeripheryUtils.convertTLtoAXI(mem)(outermostParams)
-    axi_sync.ar.bits.cache := UInt("b0011")
-    axi_sync.aw.bits.cache := UInt("b0011")
+    axi_sync.ar.bits.cache := CACHE_NORMAL_NOCACHE_BUF
+    axi_sync.aw.bits.cache := CACHE_NORMAL_NOCACHE_BUF
     axi <> (
       if (!p(AsyncMemChannels)) axi_sync
       else AsyncNastiTo(io.mem_clk.get(idx), io.mem_rst.get(idx), axi_sync)
@@ -178,7 +179,7 @@ trait PeripheryMasterMemModule extends HasPeripheryParameters {
   }
 
   (io.mem_tl zip coreplex.io.master.mem) foreach { case (tl, mem) =>
-    tl <> ClientUncachedTileLinkEnqueuer(mem, 2)(outermostParams)
+    tl <> TileLinkEnqueuer(mem, 2)(outermostParams)
   }
 }
 
@@ -228,7 +229,7 @@ trait PeripheryMasterMMIOModule extends HasPeripheryParameters {
       io.mmio_ahb(idx) <> PeripheryUtils.convertTLtoAHB(mmio_ports(i), atomics = true)(outermostMMIOParams)
     } else if (mmio_tl_start <= i && i < mmio_tl_end) {
       val idx = i-mmio_tl_start
-      io.mmio_tl(idx) <> ClientUncachedTileLinkEnqueuer(mmio_ports(i), 2)(outermostMMIOParams)
+      io.mmio_tl(idx) <> TileLinkEnqueuer(mmio_ports(i), 2)(outermostMMIOParams)
     } else {
       require(false, "Unconnected external MMIO port")
     }
@@ -303,6 +304,29 @@ trait PeripheryAONModule extends HasPeripheryParameters {
 
 /////
 
+trait PeripheryBootROM extends LazyModule {
+  implicit val p: Parameters
+  val pDevices: ResourceManager[AddrMapEntry]
+
+  pDevices.add(AddrMapEntry("bootrom", MemRange(0x1000, 4096, MemAttr(AddrMapProt.RX))))
+}
+
+trait PeripheryBootROMBundle {
+  implicit val p: Parameters
+}
+
+trait PeripheryBootROMModule extends HasPeripheryParameters {
+  implicit val p: Parameters
+  val outer: PeripheryBootROM
+  val io: PeripheryBootROMBundle
+  val mmioNetwork: Option[TileLinkRecursiveInterconnect]
+
+  val bootROM = Module(new ROMSlave(GenerateBootROM(p))(innerMMIOParams))
+  bootROM.io <> mmioNetwork.get.port("bootrom")
+}
+
+/////
+
 trait PeripheryTestRAM extends LazyModule {
   implicit val p: Parameters
   val pDevices: ResourceManager[AddrMapEntry]
diff --git a/src/main/scala/rocketchip/TestHarness.scala b/src/main/scala/rocketchip/TestHarness.scala
index 15fe6c7c..9e073499 100644
--- a/src/main/scala/rocketchip/TestHarness.scala
+++ b/src/main/scala/rocketchip/TestHarness.scala
@@ -6,6 +6,7 @@ import Chisel._
 import cde.{Parameters, Field}
 import rocket.Util._
 import junctions._
+import junctions.NastiConstants._
 
 case object BuildExampleTop extends Field[Parameters => ExampleTop]
 case object SimMemLatency extends Field[Int]
@@ -117,12 +118,12 @@ class SimAXIMem(size: BigInt)(implicit p: Parameters) extends NastiModule()(p) {
 
   io.axi.b.valid := bValid
   io.axi.b.bits.id := aw.id
-  io.axi.b.bits.resp := UInt(0)
+  io.axi.b.bits.resp := RESP_OKAY
 
   io.axi.r.valid := rValid
   io.axi.r.bits.id := ar.id
   io.axi.r.bits.data := mem((ar.addr >> log2Ceil(nastiXDataBits/8))(log2Ceil(depth)-1, 0))
-  io.axi.r.bits.resp := UInt(0)
+  io.axi.r.bits.resp := RESP_OKAY
   io.axi.r.bits.last := ar.len === UInt(0)
 }
 
@@ -175,10 +176,22 @@ class JTAGVPI(implicit val p: Parameters) extends BlackBox {
   }
 }
 
-object LatencyPipe {
+class LatencyPipe[T <: Data](typ: T, latency: Int) extends Module {
+  val io = new Bundle {
+    val in = Decoupled(typ).flip
+    val out = Decoupled(typ)
+  }
+
   def doN[T](n: Int, func: T => T, in: T): T =
     (0 until n).foldLeft(in)((last, _) => func(last))
 
-  def apply[T <: Data](in: DecoupledIO[T], latency: Int): DecoupledIO[T] =
-    doN(latency, (last: DecoupledIO[T]) => Queue(last, 1, pipe=true), in)
+  io.out <> doN(latency, (last: DecoupledIO[T]) => Queue(last, 1, pipe=true), io.in)
+}
+
+object LatencyPipe {
+  def apply[T <: Data](in: DecoupledIO[T], latency: Int): DecoupledIO[T] = {
+    val pipe = Module(new LatencyPipe(in.bits, latency))
+    pipe.io.in <> in
+    pipe.io.out
+  }
 }
diff --git a/src/main/scala/rocketchip/Top.scala b/src/main/scala/rocketchip/Top.scala
index ca239673..c56ffc46 100644
--- a/src/main/scala/rocketchip/Top.scala
+++ b/src/main/scala/rocketchip/Top.scala
@@ -75,17 +75,17 @@ class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L,
 
 /** Example Top with Periphery */
 class ExampleTop(p: Parameters) extends BaseTop(p)
-    with PeripheryDebug with PeripheryExtInterrupts with PeripheryAON
+    with PeripheryBootROM with PeripheryDebug with PeripheryExtInterrupts with PeripheryAON
     with PeripheryMasterMem with PeripheryMasterMMIO with PeripherySlave {
   override lazy val module = Module(new ExampleTopModule(p, this, new ExampleTopBundle(p, _)))
 }
 
 class ExampleTopBundle(p: Parameters, c: Coreplex) extends BaseTopBundle(p, c)
-    with PeripheryDebugBundle with PeripheryExtInterruptsBundle with PeripheryAONBundle
+    with PeripheryBootROMBundle with PeripheryDebugBundle with PeripheryExtInterruptsBundle with PeripheryAONBundle
     with PeripheryMasterMemBundle with PeripheryMasterMMIOBundle with PeripherySlaveBundle
 
 class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters, l: L, b: Coreplex => B) extends BaseTopModule(p, l, b)
-    with PeripheryDebugModule with PeripheryExtInterruptsModule with PeripheryAONModule
+    with PeripheryBootROMModule with PeripheryDebugModule with PeripheryExtInterruptsModule with PeripheryAONModule
     with PeripheryMasterMemModule with PeripheryMasterMMIOModule with PeripherySlaveModule
 
 /** Example Top with TestRAM */
diff --git a/src/main/scala/rocketchip/UnitTest.scala b/src/main/scala/rocketchip/UnitTest.scala
index d310caac..1d23e3c7 100644
--- a/src/main/scala/rocketchip/UnitTest.scala
+++ b/src/main/scala/rocketchip/UnitTest.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package rocketchip.utest
+package rocketchip
 
 import scala.collection.mutable.LinkedHashSet
 
@@ -31,7 +31,7 @@ class WithUnitTest extends Config(
 
 class UnitTestConfig extends Config(new WithUnitTest ++ new BaseConfig)
 
-class TestHarness(implicit val p: Parameters) extends Module {
+class UnitTestHarness(implicit val p: Parameters) extends Module {
   val io = new Bundle {
     val success = Bool(OUTPUT)
   }
diff --git a/src/main/scala/rocketchip/Utils.scala b/src/main/scala/rocketchip/Utils.scala
index b07a91b2..fb0d8676 100644
--- a/src/main/scala/rocketchip/Utils.scala
+++ b/src/main/scala/rocketchip/Utils.scala
@@ -9,6 +9,9 @@ import rocket._
 import rocket.Util._
 import coreplex._
 
+import java.nio.file.{Files, Paths}
+import java.nio.{ByteBuffer, ByteOrder}
+
 class RangeManager {
   private var finalized = false
   private val l = collection.mutable.HashMap[String, Int]()
@@ -52,7 +55,6 @@ object GenerateGlobalAddrMap {
     lazy val intIOAddrMap: AddrMap = {
       val entries = collection.mutable.ArrayBuffer[AddrMapEntry]()
       entries += AddrMapEntry("debug", MemSize(4096, MemAttr(AddrMapProt.RWX)))
-      entries += AddrMapEntry("bootrom", MemSize(4096, MemAttr(AddrMapProt.RX)))
       entries += AddrMapEntry("plic", MemRange(0x40000000, 0x4000000, MemAttr(AddrMapProt.RW)))
       if (p(DataScratchpadSize) > 0) { // TODO heterogeneous tiles
         require(p(NTiles) == 1) // TODO relax this
@@ -146,3 +148,26 @@ object GenerateConfigString {
     res.toString
   }
 }
+
+object GenerateBootROM {
+  def apply(p: Parameters) = {
+    val romdata = Files.readAllBytes(Paths.get(p(BootROMFile)))
+    val rom = ByteBuffer.wrap(romdata)
+
+    rom.order(ByteOrder.LITTLE_ENDIAN)
+
+    // for now, have the reset vector jump straight to memory
+    val memBase = (
+      if (p(GlobalAddrMap).get contains "mem") p(GlobalAddrMap).get("mem")
+      else p(GlobalAddrMap).get("io:int:dmem0")
+    ).start
+    val resetToMemDist = memBase - p(ResetVector)
+    require(resetToMemDist == (resetToMemDist.toInt >> 12 << 12))
+    val configStringAddr = p(ResetVector).toInt + rom.capacity
+
+    require(rom.getInt(12) == 0,
+      "Config string address position should not be occupied by code")
+    rom.putInt(12, configStringAddr)
+    rom.array() ++ (p(ConfigString).get.getBytes.toSeq)
+  }
+}
diff --git a/src/main/scala/uncore/converters/Nasti.scala b/src/main/scala/uncore/converters/Nasti.scala
index 0743b488..3477e976 100644
--- a/src/main/scala/uncore/converters/Nasti.scala
+++ b/src/main/scala/uncore/converters/Nasti.scala
@@ -3,6 +3,7 @@ package uncore.converters
 import Chisel._
 import junctions._
 import util.{ReorderQueue, DecoupledHelper}
+import junctions.NastiConstants._
 import uncore.tilelink._
 import uncore.constants._
 import cde.Parameters
@@ -234,8 +235,8 @@ class NastiIOTileLinkIOConverter(implicit p: Parameters) extends TLModule()(p)
     data = Bits(0))
   assert(!gnt_arb.io.in(1).valid || put_id_mapper.io.resp.matches, "NASTI tag error")
 
-  assert(!io.nasti.r.valid || io.nasti.r.bits.resp === UInt(0), "NASTI read error")
-  assert(!io.nasti.b.valid || io.nasti.b.bits.resp === UInt(0), "NASTI write error")
+  assert(!io.nasti.r.valid || io.nasti.r.bits.resp === RESP_OKAY, "NASTI read error")
+  assert(!io.nasti.b.valid || io.nasti.b.bits.resp === RESP_OKAY, "NASTI write error")
 }
 
 class TileLinkIONastiIOConverter(implicit p: Parameters) extends TLModule()(p)
diff --git a/src/main/scala/uncore/converters/Smi.scala b/src/main/scala/uncore/converters/Smi.scala
deleted file mode 100644
index 8fa2fa92..00000000
--- a/src/main/scala/uncore/converters/Smi.scala
+++ /dev/null
@@ -1,59 +0,0 @@
-// See LICENSE for details
-
-package uncore.converters
-
-import Chisel._
-import junctions._
-import uncore.tilelink._
-import cde.Parameters
-
-/** Convert TileLink protocol to Smi protocol */
-class SmiIOTileLinkIOConverter(val dataWidth: Int, val addrWidth: Int)
-                              (implicit p: Parameters) extends Module {
-  val io = new Bundle {
-    val tl = (new ClientUncachedTileLinkIO).flip
-    val smi = new SmiIO(dataWidth, addrWidth)
-  }
-
-  def decoupledNastiConnect(outer: NastiIO, inner: NastiIO) {
-    outer.ar <> Queue(inner.ar)
-    outer.aw <> Queue(inner.aw)
-    outer.w  <> Queue(inner.w)
-    inner.r  <> Queue(outer.r)
-    inner.b  <> Queue(outer.b)
-  }
-
-  val tl2nasti  = Module(new NastiIOTileLinkIOConverter())
-  val nasti2smi = Module(new SmiIONastiIOConverter(dataWidth, addrWidth))
-
-  tl2nasti.io.tl <> io.tl
-  decoupledNastiConnect(nasti2smi.io.nasti, tl2nasti.io.nasti)
-  io.smi <> nasti2smi.io.smi
-}
-
-class SmiConverterTest(implicit val p: Parameters) extends unittest.UnitTest
-    with HasTileLinkParameters {
-  val outermostParams = p.alterPartial({ case TLId => "Outermost" })
-
-  val smiWidth = 32
-  val smiDepth = 64
-  val tlDepth = (smiWidth * smiDepth) / tlDataBits
-
-  val smimem = Module(new SmiMem(smiWidth, smiDepth))
-  val conv = Module(new SmiIOTileLinkIOConverter(
-    smiWidth, log2Up(smiDepth))(outermostParams))
-  val driver = Module(new DriverSet(
-    (driverParams: Parameters) => {
-      implicit val p = driverParams
-      Seq(
-        Module(new PutSweepDriver(tlDepth)),
-        Module(new PutMaskDriver(smiWidth / 8)),
-        Module(new PutBlockSweepDriver(tlDepth / tlDataBeats)),
-        Module(new GetMultiWidthDriver))
-    })(outermostParams))
-
-  conv.io.tl <> driver.io.mem
-  smimem.io <> conv.io.smi
-  driver.io.start := io.start
-  io.finished := driver.io.finished
-}
diff --git a/src/main/scala/uncore/util/Enqueuer.scala b/src/main/scala/uncore/util/Enqueuer.scala
index 0e3b9e8a..71c1d8c1 100644
--- a/src/main/scala/uncore/util/Enqueuer.scala
+++ b/src/main/scala/uncore/util/Enqueuer.scala
@@ -30,6 +30,23 @@ object TileLinkEnqueuer {
   def apply(in: TileLinkIO, depth: Int)(implicit p: Parameters): TileLinkIO = {
     apply(in, TileLinkDepths(depth, depth, depth, depth, depth))
   }
+
+  def apply(in: ClientTileLinkIO, depths: TileLinkDepths)(implicit p: Parameters): ClientTileLinkIO = {
+    val t = Module(new ClientTileLinkEnqueuer(depths))
+    t.io.inner <> in
+    t.io.outer
+  }
+  def apply(in: ClientTileLinkIO, depth: Int)(implicit p: Parameters): ClientTileLinkIO = {
+    apply(in, TileLinkDepths(depth, depth, depth, depth, depth))
+  }
+  def apply(in: ClientUncachedTileLinkIO, depths: UncachedTileLinkDepths)(implicit p: Parameters): ClientUncachedTileLinkIO = {
+    val t = Module(new ClientUncachedTileLinkEnqueuer(depths))
+    t.io.inner <> in
+    t.io.outer
+  }
+  def apply(in: ClientUncachedTileLinkIO, depth: Int)(implicit p: Parameters): ClientUncachedTileLinkIO = {
+    apply(in, UncachedTileLinkDepths(depth, depth))
+  }
 }
 
 class ClientTileLinkEnqueuer(depths: TileLinkDepths)(implicit p: Parameters) extends Module {
@@ -45,17 +62,6 @@ class ClientTileLinkEnqueuer(depths: TileLinkDepths)(implicit p: Parameters) ext
   io.outer.finish  <> (if(depths.fin > 0) Queue(io.inner.finish,  depths.fin) else io.inner.finish)
 }
 
-object ClientTileLinkEnqueuer {
-  def apply(in: ClientTileLinkIO, depths: TileLinkDepths)(implicit p: Parameters): ClientTileLinkIO = {
-    val t = Module(new ClientTileLinkEnqueuer(depths))
-    t.io.inner <> in
-    t.io.outer
-  }
-  def apply(in: ClientTileLinkIO, depth: Int)(implicit p: Parameters): ClientTileLinkIO = {
-    apply(in, TileLinkDepths(depth, depth, depth, depth, depth))
-  }
-}
-
 class ClientUncachedTileLinkEnqueuer(depths: UncachedTileLinkDepths)(implicit p: Parameters) extends Module {
   val io = new Bundle {
     val inner = new ClientUncachedTileLinkIO().flip
@@ -65,14 +71,3 @@ class ClientUncachedTileLinkEnqueuer(depths: UncachedTileLinkDepths)(implicit p:
   io.outer.acquire <> (if(depths.acq > 0) Queue(io.inner.acquire, depths.acq) else io.inner.acquire)
   io.inner.grant   <> (if(depths.gnt > 0) Queue(io.outer.grant,   depths.gnt) else io.outer.grant)
 }
-
-object ClientUncachedTileLinkEnqueuer {
-  def apply(in: ClientUncachedTileLinkIO, depths: UncachedTileLinkDepths)(implicit p: Parameters): ClientUncachedTileLinkIO = {
-    val t = Module(new ClientUncachedTileLinkEnqueuer(depths))
-    t.io.inner <> in
-    t.io.outer
-  }
-  def apply(in: ClientUncachedTileLinkIO, depth: Int)(implicit p: Parameters): ClientUncachedTileLinkIO = {
-    apply(in, UncachedTileLinkDepths(depth, depth))
-  }
-}
diff --git a/src/main/scala/unittest/TempListOfTests.scala b/src/main/scala/unittest/TempListOfTests.scala
index 5cef9920..d770943a 100644
--- a/src/main/scala/unittest/TempListOfTests.scala
+++ b/src/main/scala/unittest/TempListOfTests.scala
@@ -14,7 +14,6 @@ object JunctionsUnitTests {
 object UncoreUnitTests {
   def apply(implicit p: Parameters): Seq[UnitTest] =
     Seq(
-      Module(new uncore.converters.SmiConverterTest),
       Module(new uncore.devices.ROMSlaveTest),
       Module(new uncore.devices.TileLinkRAMTest),
       Module(new uncore.tilelink2.TLFuzzRAMTest))
diff --git a/vsim/Makefrag b/vsim/Makefrag
index 31ee449b..ba537d85 100644
--- a/vsim/Makefrag
+++ b/vsim/Makefrag
@@ -51,6 +51,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
 	$(RISCV)/lib/libfesvr.so \
 	-sverilog \
 	+incdir+$(generated_dir) \
+	+define+MODEL=$(MODEL) \
 	+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \
 	+define+PRINTF_COND=$(TB).printf_cond \
 	+define+STOP_COND=!$(TB).reset \
diff --git a/vsim/Makefrag-verilog b/vsim/Makefrag-verilog
index 9cab4cc9..00785e33 100644
--- a/vsim/Makefrag-verilog
+++ b/vsim/Makefrag-verilog
@@ -5,6 +5,10 @@
 # files.
 .SECONDARY: $(generated_dir)/$(MODEL).$(CONFIG).fir
 
+firrtl: $(generated_dir)/$(MODEL).$(CONFIG).fir
+
+.PHONY: firrtl
+
 $(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)/%.prm: $(chisel_srcs) $(bootrom_img)
 	mkdir -p $(dir $@)
 	cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(notdir $*) $(CFG_PROJECT) $(CONFIG)"
diff --git a/vsrc/TestDriver.v b/vsrc/TestDriver.v
index 4d5bd632..305593c0 100644
--- a/vsrc/TestDriver.v
+++ b/vsrc/TestDriver.v
@@ -87,7 +87,7 @@ module TestDriver;
     end
   end
 
-  TestHarness testHarness(
+  `MODEL testHarness(
     .clk(clk),
     .reset(reset),
     .io_success(success)