riscv/rocket-chip
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rocketchip: re-enable testing of atomics

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This commit is contained in:
Wesley W. Terpstra
2016-09-21 23:07:54 -07:00
parent e5da3eb8bb
commit 0a3718881f
2 changed files with 3 additions and 3 deletions
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src/main/scala/rocketchip/BaseTop.scala
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@@ -49,7 +49,7 @@ abstract class BaseTop(q: Parameters) extends LazyModule {
val legacy = LazyModule(new TLLegacy()(p.alterPartial({ case TLId => "L2toMMIO" })))
peripheryBus.node := TLBuffer(TLWidthWidget(TLHintHandler(legacy.node), legacy.tlDataBytes))
peripheryBus.node := TLWidthWidget(TLBuffer(TLAtomicAutomata()(TLHintHandler(legacy.node))), legacy.tlDataBytes)
}
abstract class BaseTopBundle(val p: Parameters) extends Bundle {