riscv/rocket-chip
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Merge remote-tracking branch 'origin/master' into auto-diplomacy-bundles

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Wesley W. Terpstra
2017-09-27 16:28:10 -07:00
parent feae216f05 33b46af806
commit 0a287df0f7
6 changed files with 52 additions and 29 deletions
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src/main/scala/rocket/ICache.scala
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@ -175,15 +175,13 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
val tag_array = SeqMem(nSets, Vec(nWays, UInt(width = tECC.width(1 + tagBits))))
val tag_rdata = tag_array.read(s0_vaddr(untagBits-1,blockOffBits), !refill_done && s0_valid)
val accruedRefillError = Reg(Bool())
val refillError = tl_out.d.bits.error || (refill_cnt > 0 && accruedRefillError)
when (refill_done) {
val enc_tag = tECC.encode(Cat(refillError, refill_tag))
val enc_tag = tECC.encode(Cat(tl_out.d.bits.error, refill_tag))
tag_array.write(refill_idx, Vec.fill(nWays)(enc_tag), Seq.tabulate(nWays)(repl_way === _))
}
val vb_array = Reg(init=Bits(0, nSets*nWays))
when (refill_one_beat) {
accruedRefillError := refillError
// clear bit when refill starts so hit-under-miss doesn't fetch bad data
vb_array := vb_array.bitSet(Cat(repl_way, refill_idx), refill_done && !invalidated)
}