diff --git a/groundtest/src/main/scala/comparator.scala b/groundtest/src/main/scala/comparator.scala
index 76aac45a..a6f78b55 100644
--- a/groundtest/src/main/scala/comparator.scala
+++ b/groundtest/src/main/scala/comparator.scala
@@ -137,7 +137,7 @@ class ComparatorSource(implicit val p: Parameters) extends Module
     // Override whatever else we were going to do if we are wiping
     PutBlock(client_xact_id, wipe_addr_block, UInt(0), data),
     // Generate a random a_type
-    MuxBundle(a_type_sel, get, Array(
+    MuxLookup(a_type_sel, get, Array(
       UInt("b000") -> get,
       UInt("b001") -> getBlock,
       UInt("b010") -> put,
diff --git a/groundtest/src/main/scala/regression.scala b/groundtest/src/main/scala/regression.scala
index c0290277..375a3e1d 100644
--- a/groundtest/src/main/scala/regression.scala
+++ b/groundtest/src/main/scala/regression.scala
@@ -152,7 +152,7 @@ class NoAllocPutHitRegression(implicit p: Parameters) extends Regression()(p) {
     addr_block = addr_block)
 
   io.mem.acquire.valid := (state === s_prefetch) || (state === s_get) || (state === s_put)
-  io.mem.acquire.bits := MuxBundle(get_acq, Seq(
+  io.mem.acquire.bits := MuxCase(get_acq, Seq(
     (state === s_prefetch) -> prefetch_acq,
     (state === s_put) -> put_acq))
   io.mem.grant.ready := Bool(true)
@@ -228,7 +228,7 @@ class MixedAllocPutRegression(implicit p: Parameters) extends Regression()(p) {
     addr_beat = test_beat(get_acq_id))
 
   io.mem.acquire.valid := (state === s_pf_send) || (state === s_put_send) || (state === s_get_send)
-  io.mem.acquire.bits := MuxBundle(state, pf_acquire, Seq(
+  io.mem.acquire.bits := MuxLookup(state, pf_acquire, Seq(
     s_put_send -> put_acquire,
     s_get_send -> get_acquire))
   io.mem.grant.ready := (state === s_pf_wait) || (state === s_put_wait) || (state === s_get_wait)
diff --git a/groundtest/src/main/scala/unittest.scala b/groundtest/src/main/scala/unittest.scala
index b8eb49c0..cddf7e56 100644
--- a/groundtest/src/main/scala/unittest.scala
+++ b/groundtest/src/main/scala/unittest.scala
@@ -632,7 +632,7 @@ class BRAMSlaveDriver(implicit val p: Parameters) extends Module
     state === s_pf_stall || state === s_put_stall || state === s_get_stall, 4)
 
   io.mem.acquire.valid := (state === s_pf_req) || (state === s_put_req) || (state === s_get_req)
-  io.mem.acquire.bits := MuxBundle(state, get_acquire, Seq(
+  io.mem.acquire.bits := MuxLookup(state, get_acquire, Seq(
     s_pf_req -> pf_acquire,
     s_put_req -> put_acquire))
   io.mem.grant.ready := (state === s_pf_resp) || (state === s_put_resp) || (state === s_get_resp)