riscv/rocket-chip
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Add option to remove basic counters (mcycle/minstret)

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This commit is contained in:
Andrew Waterman 2017-09-20 19:15:36 -07:00
parent ab0821f25b
commit 09468a272b
3 changed files with 33 additions and 26 deletions
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39
src/main/scala/rocket/CSR.scala
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@ -342,8 +342,6 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
CSRs.mimpid -> UInt(0), CSRs.mimpid -> UInt(0),
CSRs.marchid -> UInt(0), CSRs.marchid -> UInt(0),
CSRs.mvendorid -> UInt(0), CSRs.mvendorid -> UInt(0),
CSRs.mcycle -> reg_cycle,
CSRs.minstret -> reg_instret,
CSRs.misa -> reg_misa, CSRs.misa -> reg_misa,
CSRs.mstatus -> read_mstatus, CSRs.mstatus -> read_mstatus,
CSRs.mtvec -> reg_mtvec, CSRs.mtvec -> reg_mtvec,
@ -371,6 +369,10 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
if (usingFPU) if (usingFPU)
read_mapping ++= fp_csrs read_mapping ++= fp_csrs
if (coreParams.haveBasicCounters) {
read_mapping += CSRs.mcycle -> reg_cycle
read_mapping += CSRs.minstret -> reg_instret
for (((e, c), i) <- (reg_hpmevent.padTo(CSR.nHPM, UInt(0)) for (((e, c), i) <- (reg_hpmevent.padTo(CSR.nHPM, UInt(0))
zip reg_hpmcounter.map(x => x: UInt).padTo(CSR.nHPM, UInt(0))) zipWithIndex) { zip reg_hpmcounter.map(x => x: UInt).padTo(CSR.nHPM, UInt(0))) zipWithIndex) {
read_mapping += (i + CSR.firstHPE) -> e // mhpmeventN read_mapping += (i + CSR.firstHPE) -> e // mhpmeventN
@ -382,6 +384,22 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
} }
} }
if (usingUser) {
read_mapping += CSRs.mcounteren -> reg_mcounteren
read_mapping += CSRs.cycle -> reg_cycle
read_mapping += CSRs.instret -> reg_instret
}
if (xLen == 32) {
read_mapping += CSRs.mcycleh -> (reg_cycle >> 32)
read_mapping += CSRs.minstreth -> (reg_instret >> 32)
if (usingUser) {
read_mapping += CSRs.cycleh -> (reg_cycle >> 32)
read_mapping += CSRs.instreth -> (reg_instret >> 32)
}
}
}
if (usingVM) { if (usingVM) {
val read_sie = reg_mie & reg_mideleg val read_sie = reg_mie & reg_mideleg
val read_sip = read_mip & reg_mideleg val read_sip = read_mip & reg_mideleg
@ -411,21 +429,6 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
read_mapping += CSRs.medeleg -> reg_medeleg read_mapping += CSRs.medeleg -> reg_medeleg
} }
if (usingUser) {
read_mapping += CSRs.mcounteren -> reg_mcounteren
read_mapping += CSRs.cycle -> reg_cycle
read_mapping += CSRs.instret -> reg_instret
}
if (xLen == 32) {
read_mapping += CSRs.mcycleh -> (reg_cycle >> 32)
read_mapping += CSRs.minstreth -> (reg_instret >> 32)
if (usingUser) {
read_mapping += CSRs.cycleh -> (reg_cycle >> 32)
read_mapping += CSRs.instreth -> (reg_instret >> 32)
}
}
val pmpCfgPerCSR = xLen / new PMPConfig().getWidth val pmpCfgPerCSR = xLen / new PMPConfig().getWidth
def pmpCfgIndex(i: Int) = (xLen / 32) * (i / pmpCfgPerCSR) def pmpCfgIndex(i: Int) = (xLen / 32) * (i / pmpCfgPerCSR)
if (reg_pmp.nonEmpty) { if (reg_pmp.nonEmpty) {
@ -629,8 +632,10 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
writeCounter(i + CSR.firstMHPC, c, wdata) writeCounter(i + CSR.firstMHPC, c, wdata)
when (decoded_addr(i + CSR.firstHPE)) { e := perfEventSets.maskEventSelector(wdata) } when (decoded_addr(i + CSR.firstHPE)) { e := perfEventSets.maskEventSelector(wdata) }
} }
if (coreParams.haveBasicCounters) {
writeCounter(CSRs.mcycle, reg_cycle, wdata) writeCounter(CSRs.mcycle, reg_cycle, wdata)
writeCounter(CSRs.minstret, reg_instret, wdata) writeCounter(CSRs.minstret, reg_instret, wdata)
}
if (usingFPU) { if (usingFPU) {
when (decoded_addr(CSRs.fflags)) { reg_fflags := wdata } when (decoded_addr(CSRs.fflags)) { reg_fflags := wdata }

1
src/main/scala/rocket/RocketCore.scala
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@ -23,6 +23,7 @@ case class RocketCoreParams(
nBreakpoints: Int = 1, nBreakpoints: Int = 1,
nPMPs: Int = 8, nPMPs: Int = 8,
nPerfCounters: Int = 0, nPerfCounters: Int = 0,
haveBasicCounters: Boolean = true,
nL2TLBEntries: Int = 0, nL2TLBEntries: Int = 0,
mtvecInit: Option[BigInt] = Some(BigInt(0)), mtvecInit: Option[BigInt] = Some(BigInt(0)),
mtvecWritable: Boolean = true, mtvecWritable: Boolean = true,

1
src/main/scala/tile/Core.scala
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@ -28,6 +28,7 @@ trait CoreParams {
val nPMPs: Int val nPMPs: Int
val nBreakpoints: Int val nBreakpoints: Int
val nPerfCounters: Int val nPerfCounters: Int
val haveBasicCounters: Boolean
val nL2TLBEntries: Int val nL2TLBEntries: Int
val mtvecInit: Option[BigInt] val mtvecInit: Option[BigInt]
val mtvecWritable: Boolean val mtvecWritable: Boolean