riscv/rocket-chip
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refactor cache params

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This commit is contained in:
Henry Cook
2014-12-17 14:28:05 -08:00
parent d29793d1f7
commit 08dcf4c6ca
2 changed files with 31 additions and 30 deletions
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rocket/src/main/scala/icache.scala
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@ -13,6 +13,8 @@ abstract trait L1CacheParameters extends CacheParameters with CoreParameters {
val co = params(TLCoherence)
val code = params(ECCCode).getOrElse(new IdentityCode)
val outerDataBeats = params(TLDataBeats)
val refillCyclesPerBeat = params(TLDataBits)/rowBits
val refillCycles = refillCyclesPerBeat*outerDataBeats
}
abstract trait FrontendParameters extends L1CacheParameters