riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

RegFieldDesc: Clean up both descriptions and JSON presentations

Browse Source
This commit is contained in:
Megan Wachs
2018-02-11 23:57:57 -08:00
parent 5ab4204e8a
commit 08acbe1a29
4 changed files with 28 additions and 28 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/devices/tilelink/Clint.scala
View File

@ -83,9 +83,9 @@ class CoreplexLocalInterrupter(params: ClintParams)(implicit p: Parameters) exte
*/
node.regmap(
0 -> RegFieldGroup ("msip", Some("MSIP Bits"), ipi.zipWithIndex.map{ case (r, i) => RegField(ipiWidth, r, RegFieldDesc(s"msip_$i", "MSIP bit for Hart $i", reset=Some(0)))}),
0 -> RegFieldGroup ("msip", Some("MSIP Bits"), ipi.zipWithIndex.map{ case (r, i) => RegField(ipiWidth, r, RegFieldDesc(s"msip_$i", s"MSIP bit for Hart $i", reset=Some(0)))}),
timecmpOffset(0) -> timecmp.zipWithIndex.flatMap{ case (t, i) =>
RegFieldGroup(s"mtimecmp_$i", Some(s"MTIMECMP for hart $i"), RegField.bytes(t, Some(RegFieldDesc("mtimecmp_$i", "", reset=None))))},
RegFieldGroup(s"mtimecmp_$i", Some(s"MTIMECMP for hart $i"), RegField.bytes(t, Some(RegFieldDesc(s"mtimecmp_$i", "", reset=None))))},
timeOffset -> RegFieldGroup("mtime", Some("Timer Register"), RegField.bytes(time, Some(RegFieldDesc("mtime", "", reset=Some(0)))))
)
}

9
src/main/scala/devices/tilelink/Plic.scala
View File

@ -179,8 +179,8 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
val enableRegFields = enables.zipWithIndex.map { case (e, i) =>
PLICConsts.enableBase(i) -> RegFieldGroup("enable", Some("Enable bits for each interrupt source. 1 bit for each interrupt source."),
e.map(b => RegField(1, b, RegFieldDesc(s"enable_$i", "Enable interrupt and claim for source $i", reset=None))))
PLICConsts.enableBase(i) -> RegFieldGroup(s"enables_${i}", Some("Enable bits for each interrupt source for target $i. 1 bit for each interrupt source."),
e.zipWithIndex.map{case (b, j) => RegField(1, b, RegFieldDesc(s"enable_$i_$j", s"Enable interrupt for source $j for target $i.", reset=None))})
}
// When a hart reads a claim/complete register, then the
@ -232,8 +232,9 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
completer(i) := valid && enables(i)(completerDev)
Bool(true)
},
Some(RegFieldDesc(s"claim_complete_$i", ("Claim/Complete register for Target $i. Reading this register returns the claimed interrupt number and makes it no longer pending." +
"Writing the interrupt number back completes the interrupt."),
Some(RegFieldDesc(s"claim_complete_$i",
s"Claim/Complete register for Target $i. Reading this register returns the claimed interrupt number and makes it no longer pending." +
s"Writing the interrupt number back completes the interrupt.",
reset = None,
access = RegFieldAccessType.RWSPECIAL))
)