riscv/rocket-chip
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fix DRAMSideLLCNull entries

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This commit is contained in:
Yunsup Lee 2013-08-24 13:20:38 -07:00
parent 1e3ac0afa9
commit 0884bc9789
1 changed files with 4 additions and 4 deletions
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8
src/main/scala/RocketChip.scala
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@ -16,10 +16,12 @@ object DummyTopLevelConstants {
val ENABLE_CLEAN_EXCLUSIVE = true val ENABLE_CLEAN_EXCLUSIVE = true
val HAS_VEC = true val HAS_VEC = true
val NL2_REL_XACTS = 1 val NL2_REL_XACTS = 1
val NL2_ACQ_XACTS = 8 val NL2_ACQ_XACTS = 7
val NMSHRS = 2 val NMSHRS = 2
} }
import DummyTopLevelConstants._
object ReferenceChipBackend { object ReferenceChipBackend {
val initMap = new HashMap[Component, Bool]() val initMap = new HashMap[Component, Bool]()
} }
@ -91,7 +93,7 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge
val llc_tag_leaf = Mem(512, seqRead = true) { Bits(width = 152) } val llc_tag_leaf = Mem(512, seqRead = true) { Bits(width = 152) }
val llc_data_leaf = Mem(4096, seqRead = true) { Bits(width = 64) } val llc_data_leaf = Mem(4096, seqRead = true) { Bits(width = 64) }
//val llc = new DRAMSideLLC(512, 8, 4, llc_tag_leaf, llc_data_leaf) //val llc = new DRAMSideLLC(512, 8, 4, llc_tag_leaf, llc_data_leaf)
val llc = new DRAMSideLLCNull(8, REFILL_CYCLES) val llc = new DRAMSideLLCNull(NL2_REL_XACTS+NL2_ACQ_XACTS, REFILL_CYCLES)
val mem_serdes = new MemSerdes(htif_width) val mem_serdes = new MemSerdes(htif_width)
require(clientEndpoints.length == ln.nClients) require(clientEndpoints.length == ln.nClients)
@ -222,8 +224,6 @@ class VLSITopIO(htifWidth: Int) extends TopIO(htifWidth) {
val out_mem_valid = Bool(OUTPUT) val out_mem_valid = Bool(OUTPUT)
} }
import DummyTopLevelConstants._
class MemDessert extends Component { class MemDessert extends Component {
val io = new MemDesserIO(HTIF_WIDTH) val io = new MemDesserIO(HTIF_WIDTH)
val x = new MemDesser(HTIF_WIDTH) val x = new MemDesser(HTIF_WIDTH)