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diplomacy Nodes: remove useless indirection

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This commit is contained in:
Wesley W. Terpstra 2016-10-25 17:42:00 -07:00
parent ec2d23b8b7
commit 082f338432
1 changed files with 5 additions and 10 deletions
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15
src/main/scala/diplomacy/Nodes.scala
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@ -94,7 +94,7 @@ trait InwardNode[DI, UI, BI <: Data] extends BaseNode with InwardNodeHandle[DI,
protected[diplomacy] lazy val iPorts = { iRealized = true; reqI(); accPI.result() } protected[diplomacy] lazy val iPorts = { iRealized = true; reqI(); accPI.result() }
protected[diplomacy] val iParams: Seq[UI] protected[diplomacy] val iParams: Seq[UI]
protected[diplomacy] def iConnect: Vec[BI] val bundleIn: Vec[BI]
} }
trait OutwardNodeHandle[DO, UO, BO <: Data] trait OutwardNodeHandle[DO, UO, BO <: Data]
@ -126,7 +126,7 @@ trait OutwardNode[DO, UO, BO <: Data] extends BaseNode with OutwardNodeHandle[DO
protected[diplomacy] lazy val oPorts = { oRealized = true; reqO(); accPO.result() } protected[diplomacy] lazy val oPorts = { oRealized = true; reqO(); accPO.result() }
protected[diplomacy] val oParams: Seq[DO] protected[diplomacy] val oParams: Seq[DO]
protected[diplomacy] def oConnect: Vec[BO] val bundleOut: Vec[BO]
} }
class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
@ -164,9 +164,6 @@ class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
lazy val bundleOut = outer.bundleO(edgesOut) lazy val bundleOut = outer.bundleO(edgesOut)
lazy val bundleIn = inner.bundleI(edgesIn) lazy val bundleIn = inner.bundleI(edgesIn)
def oConnect = bundleOut
def iConnect = bundleIn
// connects the outward part of a node with the inward part of this node // connects the outward part of a node with the inward part of this node
override def := (h: OutwardNodeHandle[DI, UI, BI])(implicit sourceInfo: SourceInfo): Option[LazyModule] = { override def := (h: OutwardNodeHandle[DI, UI, BI])(implicit sourceInfo: SourceInfo): Option[LazyModule] = {
val x = this // x := y val x = this // x := y
@ -177,7 +174,7 @@ class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val o = y.oPushed val o = y.oPushed
y.oPush(i, x) y.oPush(i, x)
x.iPush(o, y) x.iPush(o, y)
val (out, binding) = inner.connect(y.oConnect(o), x.iConnect(i), x.edgesIn(i)) val (out, binding) = inner.connect(y.bundleOut(o), x.bundleIn(i), x.edgesIn(i))
LazyModule.stack.head.bindings = binding :: LazyModule.stack.head.bindings LazyModule.stack.head.bindings = binding :: LazyModule.stack.head.bindings
out out
} }
@ -195,14 +192,12 @@ class IdentityNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])
class OutputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B]) extends IdentityNode(imp) class OutputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B]) extends IdentityNode(imp)
{ {
override def oConnect = bundleOut override lazy val bundleIn = bundleOut
override def iConnect = bundleOut
} }
class InputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B]) extends IdentityNode(imp) class InputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B]) extends IdentityNode(imp)
{ {
override def oConnect = bundleIn override lazy val bundleOut = bundleIn
override def iConnect = bundleIn
} }
class SourceNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(po: PO, num: Range.Inclusive = 1 to 1) class SourceNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(po: PO, num: Range.Inclusive = 1 to 1)