From 07ad9203ff67b612f8b0676ef87d6772bca8dd25 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 5 Jun 2017 17:25:27 -0700 Subject: [PATCH] Fix FMUL sign of zero --- src/main/scala/tile/FPU.scala | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/main/scala/tile/FPU.scala b/src/main/scala/tile/FPU.scala index 54fca651..3b3f62fc 100644 --- a/src/main/scala/tile/FPU.scala +++ b/src/main/scala/tile/FPU.scala @@ -551,9 +551,8 @@ class FPUFMAPipe(val latency: Int, val t: FType)(implicit p: Parameters) extends val valid = Reg(next=io.in.valid) val in = Reg(new FPInput) when (io.in.valid) { - val signProd = io.in.bits.in1(maxType.sig + maxType.exp) ^ io.in.bits.in2(maxType.sig + maxType.exp) val one = UInt(1) << (t.sig + t.exp - 1) - val zero = signProd << (t.sig + t.exp) + val zero = UInt(1) << (t.sig + t.exp) val cmd_fma = io.in.bits.ren3 val cmd_addsub = io.in.bits.swap23 in := io.in.bits