riscv/rocket-chip
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fix long-latency writeback arbitration bug

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This commit is contained in:
Andrew Waterman
2012-01-24 00:56:47 -08:00
parent f1c355e3cd
commit 06fdf79dab
1 changed files with 2 additions and 2 deletions
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4
rocket/src/main/scala/ctrl.scala
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@@ -633,8 +633,8 @@ class rocketCtrl extends Component
// for divider, multiplier, load miss writeback
val mem_wb = Reg(io.dmem.resp_replay, resetVal = Bool(false)) // delayed for subword extension
val mul_wb = io.dpath.mul_result_val && !io.dmem.resp_replay;
val div_wb = io.dpath.div_result_val && !io.dpath.mul_result_val && !io.dmem.resp_replay;
val mul_wb = io.dpath.mul_result_val && !mem_wb;
val div_wb = io.dpath.div_result_val && !io.dpath.mul_result_val && !mem_wb;
val ctrl_stalld =
!take_pc &&