From b5ccdab514aae4b642c5a88b6c6cbe767420133b Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 22 Jan 2013 20:09:21 -0800 Subject: [PATCH 1/7] changed val names in hub to match new tilelink names --- uncore/src/uncore.scala | 462 ++++++++++++++++++++-------------------- 1 file changed, 231 insertions(+), 231 deletions(-) diff --git a/uncore/src/uncore.scala b/uncore/src/uncore.scala index 690454a1..21aaba8c 100644 --- a/uncore/src/uncore.scala +++ b/uncore/src/uncore.scala @@ -24,14 +24,14 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex val p_data = (new PipeIO) { new TrackerProbeData }.flip val can_alloc = Bool(INPUT) val grant_ack = Bool(INPUT) - val p_rep_cnt_dec = Bits(INPUT, conf.ln.nTiles) - val p_req_cnt_inc = Bits(INPUT, conf.ln.nTiles) + val release_cnt_dec = Bits(INPUT, conf.ln.nTiles) + val probe_cnt_inc = Bits(INPUT, conf.ln.nTiles) val tile_incoherent = Bits(INPUT, conf.ln.nTiles) - val p_rep_data = (new PipeIO) { new ReleaseData }.flip - val x_init_data = (new PipeIO) { new AcquireData }.flip + val release_data = (new PipeIO) { new ReleaseData }.flip + val acquire_data = (new PipeIO) { new AcquireData }.flip val sent_grant_ack = Bool(INPUT) - val p_rep_data_dep = (new PipeIO) { new TrackerDependency }.flip - val x_init_data_dep = (new PipeIO) { new TrackerDependency }.flip + val release_data_dep = (new PipeIO) { new TrackerDependency }.flip + val acquire_data_dep = (new PipeIO) { new TrackerDependency }.flip val mem_req_cmd = (new FIFOIO) { new MemReqCmd } val mem_req_data = (new FIFOIO) { new MemData } @@ -40,17 +40,17 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex val busy = Bool(OUTPUT) val addr = Bits(OUTPUT, PADDR_BITS - OFFSET_BITS) val init_client_id = Bits(OUTPUT, conf.ln.idBits) - val p_rep_client_id = Bits(OUTPUT, conf.ln.idBits) + val release_client_id = Bits(OUTPUT, conf.ln.idBits) val client_xact_id = Bits(OUTPUT, CLIENT_XACT_ID_BITS) val sharer_count = Bits(OUTPUT, conf.ln.idBits+1) val a_type = Bits(OUTPUT, ACQUIRE_TYPE_MAX_BITS) - val push_p_req = Bits(OUTPUT, conf.ln.nTiles) - val pop_p_rep = Bits(OUTPUT, conf.ln.nTiles) - val pop_p_rep_data = Bits(OUTPUT, conf.ln.nTiles) - val pop_p_rep_dep = Bits(OUTPUT, conf.ln.nTiles) - val pop_x_init = Bits(OUTPUT, conf.ln.nTiles) - val pop_x_init_data = Bits(OUTPUT, conf.ln.nTiles) - val pop_x_init_dep = Bits(OUTPUT, conf.ln.nTiles) + val push_probe = Bits(OUTPUT, conf.ln.nTiles) + val pop_release = Bits(OUTPUT, conf.ln.nTiles) + val pop_release_data = Bits(OUTPUT, conf.ln.nTiles) + val pop_release_dep = Bits(OUTPUT, conf.ln.nTiles) + val pop_acquire = Bits(OUTPUT, conf.ln.nTiles) + val pop_acquire_data = Bits(OUTPUT, conf.ln.nTiles) + val pop_acquire_dep = Bits(OUTPUT, conf.ln.nTiles) val send_grant_ack = Bool(OUTPUT) } @@ -91,19 +91,19 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex val state = Reg(resetVal = s_idle) val xact = Reg{ new Acquire } val init_client_id_ = Reg{ Bits() } - val p_rep_count = if (conf.ln.nTiles == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles))) - val p_req_flags = Reg(resetVal = Bits(0, width = conf.ln.nTiles)) - val p_rep_client_id_ = Reg{ Bits() } + val release_count = if (conf.ln.nTiles == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles))) + val probe_flags = Reg(resetVal = Bits(0, width = conf.ln.nTiles)) + val release_client_id_ = Reg{ Bits() } val x_needs_read = Reg(resetVal = Bool(false)) - val x_init_data_needs_write = Reg(resetVal = Bool(false)) - val p_rep_data_needs_write = Reg(resetVal = Bool(false)) + val acquire_data_needs_write = Reg(resetVal = Bool(false)) + val release_data_needs_write = Reg(resetVal = Bool(false)) val x_w_mem_cmd_sent = Reg(resetVal = Bool(false)) val p_w_mem_cmd_sent = Reg(resetVal = Bool(false)) val mem_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES))) val mem_cnt_next = mem_cnt + UFix(1) val mem_cnt_max = ~UFix(0, width = log2Up(REFILL_CYCLES)) - val p_req_initial_flags = Bits(width = conf.ln.nTiles) - p_req_initial_flags := Bits(0) + val probe_initial_flags = Bits(width = conf.ln.nTiles) + probe_initial_flags := Bits(0) if (conf.ln.nTiles > 1) { // issue self-probes for uncached read xacts to facilitate I$ coherence // TODO: this is hackish; figure out how to do it more systematically @@ -112,13 +112,13 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex case _ => Bool(false) } val myflag = Mux(probe_self, Bits(0), UFixToOH(io.alloc_req.bits.client_id(log2Up(conf.ln.nTiles)-1,0))) - p_req_initial_flags := ~(io.tile_incoherent | myflag) + probe_initial_flags := ~(io.tile_incoherent | myflag) } io.busy := state != s_idle io.addr := xact.addr io.init_client_id := init_client_id_ - io.p_rep_client_id := p_rep_client_id_ + io.release_client_id := release_client_id_ io.client_xact_id := xact.client_xact_id io.sharer_count := UFix(conf.ln.nTiles) // TODO: Broadcast only io.a_type := xact.a_type @@ -134,13 +134,13 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex io.probe.bits.p_type := co.getProbeType(xact.a_type, UFix(0)) io.probe.bits.master_xact_id := UFix(id) io.probe.bits.addr := xact.addr - io.push_p_req := Bits(0, width = conf.ln.nTiles) - io.pop_p_rep := Bits(0, width = conf.ln.nTiles) - io.pop_p_rep_data := Bits(0, width = conf.ln.nTiles) - io.pop_p_rep_dep := Bits(0, width = conf.ln.nTiles) - io.pop_x_init := Bits(0, width = conf.ln.nTiles) - io.pop_x_init_data := Bits(0, width = conf.ln.nTiles) - io.pop_x_init_dep := Bits(0, width = conf.ln.nTiles) + io.push_probe := Bits(0, width = conf.ln.nTiles) + io.pop_release := Bits(0, width = conf.ln.nTiles) + io.pop_release_data := Bits(0, width = conf.ln.nTiles) + io.pop_release_dep := Bits(0, width = conf.ln.nTiles) + io.pop_acquire := Bits(0, width = conf.ln.nTiles) + io.pop_acquire_data := Bits(0, width = conf.ln.nTiles) + io.pop_acquire_dep := Bits(0, width = conf.ln.nTiles) io.send_grant_ack := Bool(false) switch (state) { @@ -148,62 +148,62 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex when( io.alloc_req.valid && io.can_alloc ) { xact := io.alloc_req.bits.acquire init_client_id_ := io.alloc_req.bits.client_id - x_init_data_needs_write := co.messageHasData(io.alloc_req.bits.acquire) + acquire_data_needs_write := co.messageHasData(io.alloc_req.bits.acquire) x_needs_read := co.needsMemRead(io.alloc_req.bits.acquire.a_type, UFix(0)) - p_req_flags := p_req_initial_flags + probe_flags := probe_initial_flags mem_cnt := UFix(0) p_w_mem_cmd_sent := Bool(false) x_w_mem_cmd_sent := Bool(false) - io.pop_x_init := UFix(1) << io.alloc_req.bits.client_id + io.pop_acquire := UFix(1) << io.alloc_req.bits.client_id if(conf.ln.nTiles > 1) { - p_rep_count := PopCount(p_req_initial_flags) - state := Mux(p_req_initial_flags.orR, s_probe, s_mem) + release_count := PopCount(probe_initial_flags) + state := Mux(probe_initial_flags.orR, s_probe, s_mem) } else state := s_mem } } is(s_probe) { - when(p_req_flags.orR) { - io.push_p_req := p_req_flags + when(probe_flags.orR) { + io.push_probe := probe_flags io.probe.valid := Bool(true) } - when(io.p_req_cnt_inc.orR) { - p_req_flags := p_req_flags & ~io.p_req_cnt_inc // unflag sent reqs + when(io.probe_cnt_inc.orR) { + probe_flags := probe_flags & ~io.probe_cnt_inc // unflag sent reqs } - when(io.p_rep_cnt_dec.orR) { - val dec = PopCount(io.p_rep_cnt_dec) - io.pop_p_rep := io.p_rep_cnt_dec - if(conf.ln.nTiles > 1) p_rep_count := p_rep_count - dec - when(p_rep_count === dec) { + when(io.release_cnt_dec.orR) { + val dec = PopCount(io.release_cnt_dec) + io.pop_release := io.release_cnt_dec + if(conf.ln.nTiles > 1) release_count := release_count - dec + when(release_count === dec) { state := s_mem } } when(io.p_data.valid) { - p_rep_data_needs_write := Bool(true) - p_rep_client_id_ := io.p_data.bits.client_id + release_data_needs_write := Bool(true) + release_client_id_ := io.p_data.bits.client_id } } is(s_mem) { - when (p_rep_data_needs_write) { + when (release_data_needs_write) { doMemReqWrite(io.mem_req_cmd, io.mem_req_data, io.mem_req_lock, - io.p_rep_data, - p_rep_data_needs_write, + io.release_data, + release_data_needs_write, p_w_mem_cmd_sent, - io.pop_p_rep_data, - io.pop_p_rep_dep, - io.p_rep_data_dep.valid && (io.p_rep_data_dep.bits.master_xact_id === UFix(id)), - p_rep_client_id_) - } . elsewhen(x_init_data_needs_write) { + io.pop_release_data, + io.pop_release_dep, + io.release_data_dep.valid && (io.release_data_dep.bits.master_xact_id === UFix(id)), + release_client_id_) + } . elsewhen(acquire_data_needs_write) { doMemReqWrite(io.mem_req_cmd, io.mem_req_data, io.mem_req_lock, - io.x_init_data, - x_init_data_needs_write, + io.acquire_data, + acquire_data_needs_write, x_w_mem_cmd_sent, - io.pop_x_init_data, - io.pop_x_init_dep, - io.x_init_data_dep.valid && (io.x_init_data_dep.bits.master_xact_id === UFix(id)), + io.pop_acquire_data, + io.pop_acquire_dep, + io.acquire_data_dep.valid && (io.acquire_data_dep.bits.master_xact_id === UFix(id)), init_client_id_) } . elsewhen (x_needs_read) { doMemReqRead(io.mem_req_cmd, x_needs_read) @@ -274,22 +274,22 @@ class CoherenceHubNull(implicit conf: CoherenceHubConfiguration) extends Coheren { val co = conf.co.asInstanceOf[ThreeStateIncoherence] - val x_init = io.tiles(0).acquire - val is_write = x_init.bits.payload.a_type === co.acquireWriteback - x_init.ready := io.mem.req_cmd.ready && !(is_write && io.mem.resp.valid) //stall write req/resp to handle previous read resp - io.mem.req_cmd.valid := x_init.valid && !(is_write && io.mem.resp.valid) + val acquire = io.tiles(0).acquire + val is_write = acquire.bits.payload.a_type === co.acquireWriteback + acquire.ready := io.mem.req_cmd.ready && !(is_write && io.mem.resp.valid) //stall write req/resp to handle previous read resp + io.mem.req_cmd.valid := acquire.valid && !(is_write && io.mem.resp.valid) io.mem.req_cmd.bits.rw := is_write - io.mem.req_cmd.bits.tag := x_init.bits.payload.client_xact_id - io.mem.req_cmd.bits.addr := x_init.bits.payload.addr + io.mem.req_cmd.bits.tag := acquire.bits.payload.client_xact_id + io.mem.req_cmd.bits.addr := acquire.bits.payload.addr io.mem.req_data <> io.tiles(0).acquire_data val grant = io.tiles(0).grant grant.bits.payload.g_type := Mux(io.mem.resp.valid, co.grantData, co.grantAck) - grant.bits.payload.client_xact_id := Mux(io.mem.resp.valid, io.mem.resp.bits.tag, x_init.bits.payload.client_xact_id) + grant.bits.payload.client_xact_id := Mux(io.mem.resp.valid, io.mem.resp.bits.tag, acquire.bits.payload.client_xact_id) grant.bits.payload.master_xact_id := UFix(0) // don't care grant.bits.payload.data := io.mem.resp.bits.data grant.bits.payload.require_ack := Bool(true) - grant.valid := io.mem.resp.valid || x_init.valid && is_write && io.mem.req_cmd.ready + grant.valid := io.mem.resp.valid || acquire.valid && is_write && io.mem.req_cmd.ready io.tiles(0).abort.valid := Bool(false) io.tiles(0).grant_ack.ready := Bool(true) @@ -314,8 +314,8 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co val send_grant_ack_arr = Vec(NGLOBAL_XACTS){ Bool() } val do_free_arr = Vec(NGLOBAL_XACTS){ Bool() } - val p_rep_cnt_dec_arr = VecBuf(NGLOBAL_XACTS){ Vec(conf.ln.nTiles){ Bool()} } - val p_req_cnt_inc_arr = VecBuf(NGLOBAL_XACTS){ Vec(conf.ln.nTiles){ Bool()} } + val release_cnt_dec_arr = VecBuf(NGLOBAL_XACTS){ Vec(conf.ln.nTiles){ Bool()} } + val probe_cnt_inc_arr = VecBuf(NGLOBAL_XACTS){ Vec(conf.ln.nTiles){ Bool()} } val sent_grant_ack_arr = Vec(NGLOBAL_XACTS){ Bool() } val p_data_client_id_arr = Vec(NGLOBAL_XACTS){ Bits(width=conf.ln.idBits) } val p_data_valid_arr = Vec(NGLOBAL_XACTS){ Bool() } @@ -332,8 +332,8 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co t.grant_ack := do_free_arr(i) t.p_data.bits.client_id := p_data_client_id_arr(i) t.p_data.valid := p_data_valid_arr(i) - t.p_rep_cnt_dec := p_rep_cnt_dec_arr(i).toBits - t.p_req_cnt_inc := p_req_cnt_inc_arr(i).toBits + t.release_cnt_dec := release_cnt_dec_arr(i).toBits + t.probe_cnt_inc := probe_cnt_inc_arr(i).toBits t.tile_incoherent := io.incoherent.toBits t.sent_grant_ack := sent_grant_ack_arr(i) do_free_arr(i) := Bool(false) @@ -341,21 +341,21 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co p_data_client_id_arr(i) := Bits(0, width = conf.ln.idBits) p_data_valid_arr(i) := Bool(false) for( j <- 0 until conf.ln.nTiles) { - p_rep_cnt_dec_arr(i)(j) := Bool(false) - p_req_cnt_inc_arr(i)(j) := Bool(false) + release_cnt_dec_arr(i)(j) := Bool(false) + probe_cnt_inc_arr(i)(j) := Bool(false) } } - val p_rep_data_dep_list = List.fill(conf.ln.nTiles)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth must >= NPRIMARY - val x_init_data_dep_list = List.fill(conf.ln.nTiles)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth should >= NPRIMARY + val release_data_dep_list = List.fill(conf.ln.nTiles)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth must >= NPRIMARY + val acquire_data_dep_list = List.fill(conf.ln.nTiles)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth should >= NPRIMARY // Free finished transactions for( j <- 0 until conf.ln.nTiles ) { - val finish = io.tiles(j).grant_ack - when (finish.valid) { - do_free_arr(finish.bits.payload.master_xact_id) := Bool(true) + val ack = io.tiles(j).grant_ack + when (ack.valid) { + do_free_arr(ack.bits.payload.master_xact_id) := Bool(true) } - finish.ready := Bool(true) + ack.ready := Bool(true) } // Reply to initial requestor @@ -402,31 +402,31 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co // Handle probe replies, which may or may not have data for( j <- 0 until conf.ln.nTiles ) { - val p_rep = io.tiles(j).release - val p_rep_data = io.tiles(j).release_data - val idx = p_rep.bits.payload.master_xact_id - val pop_p_reps = trackerList.map(_.io.pop_p_rep(j).toBool) - val do_pop = foldR(pop_p_reps)(_ || _) - p_rep.ready := Bool(true) - p_rep_data_dep_list(j).io.enq.valid := p_rep.valid && co.messageHasData(p_rep.bits.payload) - p_rep_data_dep_list(j).io.enq.bits.master_xact_id := p_rep.bits.payload.master_xact_id - p_rep_data.ready := foldR(trackerList.map(_.io.pop_p_rep_data(j)))(_ || _) - when (p_rep.valid && co.messageHasData(p_rep.bits.payload)) { + val release = io.tiles(j).release + val release_data = io.tiles(j).release_data + val idx = release.bits.payload.master_xact_id + val pop_releases = trackerList.map(_.io.pop_release(j).toBool) + val do_pop = foldR(pop_releases)(_ || _) + release.ready := Bool(true) + release_data_dep_list(j).io.enq.valid := release.valid && co.messageHasData(release.bits.payload) + release_data_dep_list(j).io.enq.bits.master_xact_id := release.bits.payload.master_xact_id + release_data.ready := foldR(trackerList.map(_.io.pop_release_data(j)))(_ || _) + when (release.valid && co.messageHasData(release.bits.payload)) { p_data_valid_arr(idx) := Bool(true) p_data_client_id_arr(idx) := UFix(j) } - p_rep_data_dep_list(j).io.deq.ready := foldR(trackerList.map(_.io.pop_p_rep_dep(j).toBool))(_||_) + release_data_dep_list(j).io.deq.ready := foldR(trackerList.map(_.io.pop_release_dep(j).toBool))(_||_) } for( i <- 0 until NGLOBAL_XACTS ) { - trackerList(i).io.p_rep_data.valid := io.tiles(trackerList(i).io.p_rep_client_id).release_data.valid - trackerList(i).io.p_rep_data.bits := io.tiles(trackerList(i).io.p_rep_client_id).release_data.bits.payload + trackerList(i).io.release_data.valid := io.tiles(trackerList(i).io.release_client_id).release_data.valid + trackerList(i).io.release_data.bits := io.tiles(trackerList(i).io.release_client_id).release_data.bits.payload - trackerList(i).io.p_rep_data_dep.valid := MuxLookup(trackerList(i).io.p_rep_client_id, p_rep_data_dep_list(0).io.deq.valid, (0 until conf.ln.nTiles).map( j => UFix(j) -> p_rep_data_dep_list(j).io.deq.valid)) - trackerList(i).io.p_rep_data_dep.bits := MuxLookup(trackerList(i).io.p_rep_client_id, p_rep_data_dep_list(0).io.deq.bits, (0 until conf.ln.nTiles).map( j => UFix(j) -> p_rep_data_dep_list(j).io.deq.bits)) + trackerList(i).io.release_data_dep.valid := MuxLookup(trackerList(i).io.release_client_id, release_data_dep_list(0).io.deq.valid, (0 until conf.ln.nTiles).map( j => UFix(j) -> release_data_dep_list(j).io.deq.valid)) + trackerList(i).io.release_data_dep.bits := MuxLookup(trackerList(i).io.release_client_id, release_data_dep_list(0).io.deq.bits, (0 until conf.ln.nTiles).map( j => UFix(j) -> release_data_dep_list(j).io.deq.bits)) for( j <- 0 until conf.ln.nTiles) { - val p_rep = io.tiles(j).release - p_rep_cnt_dec_arr(i)(j) := p_rep.valid && (p_rep.bits.payload.master_xact_id === UFix(i)) + val release = io.tiles(j).release + release_cnt_dec_arr(i)(j) := release.valid && (release.bits.payload.master_xact_id === UFix(i)) } } @@ -435,31 +435,31 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co val abort_state_arr = Vec(conf.ln.nTiles) { Reg(resetVal = s_idle) } val want_to_abort_arr = Vec(conf.ln.nTiles) { Bool() } for( j <- 0 until conf.ln.nTiles ) { - val x_init = io.tiles(j).acquire - val x_init_data = io.tiles(j).acquire_data + val acquire = io.tiles(j).acquire + val acquire_data = io.tiles(j).acquire_data val x_abort = io.tiles(j).abort val abort_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES))) val conflicts = Vec(NGLOBAL_XACTS) { Bool() } for( i <- 0 until NGLOBAL_XACTS) { val t = trackerList(i).io - conflicts(i) := t.busy && x_init.valid && co.isCoherenceConflict(t.addr, x_init.bits.payload.addr) + conflicts(i) := t.busy && acquire.valid && co.isCoherenceConflict(t.addr, acquire.bits.payload.addr) } - x_abort.bits.payload.client_xact_id := x_init.bits.payload.client_xact_id - want_to_abort_arr(j) := x_init.valid && (conflicts.toBits.orR || busy_arr.toBits.andR || (!x_init_data_dep_list(j).io.enq.ready && co.messageHasData(x_init.bits.payload))) + x_abort.bits.payload.client_xact_id := acquire.bits.payload.client_xact_id + want_to_abort_arr(j) := acquire.valid && (conflicts.toBits.orR || busy_arr.toBits.andR || (!acquire_data_dep_list(j).io.enq.ready && co.messageHasData(acquire.bits.payload))) x_abort.valid := Bool(false) switch(abort_state_arr(j)) { is(s_idle) { when(want_to_abort_arr(j)) { - when(co.messageHasData(x_init.bits.payload)) { + when(co.messageHasData(acquire.bits.payload)) { abort_state_arr(j) := s_abort_drain } . otherwise { abort_state_arr(j) := s_abort_send } } } - is(s_abort_drain) { // raises x_init_data.ready below - when(x_init_data.valid) { + is(s_abort_drain) { // raises acquire_data.ready below + when(acquire_data.valid) { abort_cnt := abort_cnt + UFix(1) when(abort_cnt === ~UFix(0, width = log2Up(REFILL_CYCLES))) { abort_state_arr(j) := s_abort_send @@ -468,7 +468,7 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co } is(s_abort_send) { // nothing is dequeued for now x_abort.valid := Bool(true) - when(x_abort.ready) { // raises x_init.ready below + when(x_abort.ready) { // raises acquire.ready below abort_state_arr(j) := s_idle } } @@ -486,41 +486,41 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co trackerList(i).io.alloc_req.bits := init_arb.io.out.bits trackerList(i).io.alloc_req.valid := init_arb.io.out.valid - trackerList(i).io.x_init_data.bits := io.tiles(trackerList(i).io.init_client_id).acquire_data.bits.payload - trackerList(i).io.x_init_data.valid := io.tiles(trackerList(i).io.init_client_id).acquire_data.valid - trackerList(i).io.x_init_data_dep.bits := MuxLookup(trackerList(i).io.init_client_id, x_init_data_dep_list(0).io.deq.bits, (0 until conf.ln.nTiles).map( j => UFix(j) -> x_init_data_dep_list(j).io.deq.bits)) - trackerList(i).io.x_init_data_dep.valid := MuxLookup(trackerList(i).io.init_client_id, x_init_data_dep_list(0).io.deq.valid, (0 until conf.ln.nTiles).map( j => UFix(j) -> x_init_data_dep_list(j).io.deq.valid)) + trackerList(i).io.acquire_data.bits := io.tiles(trackerList(i).io.init_client_id).acquire_data.bits.payload + trackerList(i).io.acquire_data.valid := io.tiles(trackerList(i).io.init_client_id).acquire_data.valid + trackerList(i).io.acquire_data_dep.bits := MuxLookup(trackerList(i).io.init_client_id, acquire_data_dep_list(0).io.deq.bits, (0 until conf.ln.nTiles).map( j => UFix(j) -> acquire_data_dep_list(j).io.deq.bits)) + trackerList(i).io.acquire_data_dep.valid := MuxLookup(trackerList(i).io.init_client_id, acquire_data_dep_list(0).io.deq.valid, (0 until conf.ln.nTiles).map( j => UFix(j) -> acquire_data_dep_list(j).io.deq.valid)) } for( j <- 0 until conf.ln.nTiles ) { - val x_init = io.tiles(j).acquire - val x_init_data = io.tiles(j).acquire_data - val x_init_data_dep = x_init_data_dep_list(j).io.deq + val acquire = io.tiles(j).acquire + val acquire_data = io.tiles(j).acquire_data + val acquire_data_dep = acquire_data_dep_list(j).io.deq val x_abort = io.tiles(j).abort - init_arb.io.in(j).valid := (abort_state_arr(j) === s_idle) && !want_to_abort_arr(j) && x_init.valid - init_arb.io.in(j).bits.acquire := x_init.bits.payload + init_arb.io.in(j).valid := (abort_state_arr(j) === s_idle) && !want_to_abort_arr(j) && acquire.valid + init_arb.io.in(j).bits.acquire := acquire.bits.payload init_arb.io.in(j).bits.client_id := UFix(j) - val pop_x_inits = trackerList.map(_.io.pop_x_init(j).toBool) - val do_pop = foldR(pop_x_inits)(_||_) - x_init_data_dep_list(j).io.enq.valid := do_pop && co.messageHasData(x_init.bits.payload) && (abort_state_arr(j) === s_idle) - x_init_data_dep_list(j).io.enq.bits.master_xact_id := OHToUFix(pop_x_inits) - x_init.ready := (x_abort.valid && x_abort.ready) || do_pop - x_init_data.ready := (abort_state_arr(j) === s_abort_drain) || foldR(trackerList.map(_.io.pop_x_init_data(j).toBool))(_||_) - x_init_data_dep.ready := foldR(trackerList.map(_.io.pop_x_init_dep(j).toBool))(_||_) + val pop_acquires = trackerList.map(_.io.pop_acquire(j).toBool) + val do_pop = foldR(pop_acquires)(_||_) + acquire_data_dep_list(j).io.enq.valid := do_pop && co.messageHasData(acquire.bits.payload) && (abort_state_arr(j) === s_idle) + acquire_data_dep_list(j).io.enq.bits.master_xact_id := OHToUFix(pop_acquires) + acquire.ready := (x_abort.valid && x_abort.ready) || do_pop + acquire_data.ready := (abort_state_arr(j) === s_abort_drain) || foldR(trackerList.map(_.io.pop_acquire_data(j).toBool))(_||_) + acquire_data_dep.ready := foldR(trackerList.map(_.io.pop_acquire_dep(j).toBool))(_||_) } alloc_arb.io.out.ready := init_arb.io.out.valid // Handle probe request generation // Must arbitrate for each request port - val p_req_arb_arr = List.fill(conf.ln.nTiles)((new Arbiter(NGLOBAL_XACTS)) { new Probe() }) + val probe_arb_arr = List.fill(conf.ln.nTiles)((new Arbiter(NGLOBAL_XACTS)) { new Probe() }) for( j <- 0 until conf.ln.nTiles ) { for( i <- 0 until NGLOBAL_XACTS ) { val t = trackerList(i).io - p_req_arb_arr(j).io.in(i).bits := t.probe.bits - p_req_arb_arr(j).io.in(i).valid := t.probe.valid && t.push_p_req(j) - p_req_cnt_inc_arr(i)(j) := p_req_arb_arr(j).io.in(i).ready + probe_arb_arr(j).io.in(i).bits := t.probe.bits + probe_arb_arr(j).io.in(i).valid := t.probe.valid && t.push_probe(j) + probe_cnt_inc_arr(i)(j) := probe_arb_arr(j).io.in(i).ready } - FIFOedLogicalNetworkIOWrapper(p_req_arb_arr(j).io.out) <> io.tiles(j).probe + FIFOedLogicalNetworkIOWrapper(probe_arb_arr(j).io.out) <> io.tiles(j).probe } } @@ -538,8 +538,8 @@ class L2CoherenceAgent(implicit conf: CoherenceHubConfiguration) extends Coheren implicit val lnConf = conf.ln val co = conf.co val trackerList = (0 until NGLOBAL_XACTS).map(new XactTracker(_)) - val p_rep_data_dep_q = (new Queue(NGLOBAL_XACTS)){new TrackerDependency} // depth must >= NPRIMARY - val x_init_data_dep_q = (new Queue(NGLOBAL_XACTS)){new TrackerDependency} // depth should >= NPRIMARY + val release_data_dep_q = (new Queue(NGLOBAL_XACTS)){new TrackerDependency} // depth must >= NPRIMARY + val acquire_data_dep_q = (new Queue(NGLOBAL_XACTS)){new TrackerDependency} // depth should >= NPRIMARY for( i <- 0 until NGLOBAL_XACTS ) { val t = trackerList(i) @@ -552,49 +552,49 @@ class L2CoherenceAgent(implicit conf: CoherenceHubConfiguration) extends Coheren // Handle transaction initiation requests // Only one allocation per cycle // Init requests may or may not have data - val x_init = io.network.acquire - val x_init_data = io.network.acquire_data + val acquire = io.network.acquire + val acquire_data = io.network.acquire_data val x_abort = io.network.abort - val x_dep_deq = x_init_data_dep_q.io.deq + val x_dep_deq = acquire_data_dep_q.io.deq val s_idle :: s_abort_drain :: s_abort_send :: Nil = Enum(3){ UFix() } val abort_state = Reg(resetVal = s_idle) val abort_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES))) val any_conflict = trackerList.map(_.io.has_conflict).reduce(_||_) val all_busy = trackerList.map(_.io.busy).reduce(_&&_) - val want_to_abort = x_init.valid && (any_conflict || all_busy || (!x_init_data_dep_q.io.enq.ready && co.messageHasData(x_init.bits.payload))) + val want_to_abort = acquire.valid && (any_conflict || all_busy || (!acquire_data_dep_q.io.enq.ready && co.messageHasData(acquire.bits.payload))) val alloc_arb = (new Arbiter(NGLOBAL_XACTS)) { Bool() } for( i <- 0 until NGLOBAL_XACTS ) { alloc_arb.io.in(i).valid := !trackerList(i).io.busy - trackerList(i).io.x_init.bits := x_init.bits - trackerList(i).io.x_init.valid := (abort_state === s_idle) && !want_to_abort && x_init.valid && alloc_arb.io.in(i).ready + trackerList(i).io.acquire.bits := acquire.bits + trackerList(i).io.acquire.valid := (abort_state === s_idle) && !want_to_abort && acquire.valid && alloc_arb.io.in(i).ready - trackerList(i).io.x_init_data.bits := x_init_data.bits - trackerList(i).io.x_init_data.valid := x_init_data.valid - trackerList(i).io.x_init_data_dep.bits := x_dep_deq.bits - trackerList(i).io.x_init_data_dep.valid := x_dep_deq.valid + trackerList(i).io.acquire_data.bits := acquire_data.bits + trackerList(i).io.acquire_data.valid := acquire_data.valid + trackerList(i).io.acquire_data_dep.bits := x_dep_deq.bits + trackerList(i).io.acquire_data_dep.valid := x_dep_deq.valid } - val pop_x_init = trackerList.map(_.io.x_init.ready).reduce(_||_) - x_init.ready := (x_abort.valid && x_abort.ready) || pop_x_init - x_init_data.ready := (abort_state === s_abort_drain) || trackerList.map(_.io.x_init_data.ready).reduce(_||_) - x_init_data_dep_q.io.enq.valid := pop_x_init && co.messageHasData(x_init.bits.payload) && (abort_state === s_idle) - x_init_data_dep_q.io.enq.bits.master_xact_id := OHToUFix(trackerList.map(_.io.x_init.ready)) - x_dep_deq.ready := trackerList.map(_.io.x_init_data_dep.ready).reduce(_||_) + val pop_acquire = trackerList.map(_.io.acquire.ready).reduce(_||_) + acquire.ready := (x_abort.valid && x_abort.ready) || pop_acquire + acquire_data.ready := (abort_state === s_abort_drain) || trackerList.map(_.io.acquire_data.ready).reduce(_||_) + acquire_data_dep_q.io.enq.valid := pop_acquire && co.messageHasData(acquire.bits.payload) && (abort_state === s_idle) + acquire_data_dep_q.io.enq.bits.master_xact_id := OHToUFix(trackerList.map(_.io.acquire.ready)) + x_dep_deq.ready := trackerList.map(_.io.acquire_data_dep.ready).reduce(_||_) - alloc_arb.io.out.ready := x_init.valid + alloc_arb.io.out.ready := acquire.valid // Nack conflicting transaction init attempts - x_abort.bits.header.dst := x_init.bits.header.src - x_abort.bits.payload.client_xact_id := x_init.bits.payload.client_xact_id + x_abort.bits.header.dst := acquire.bits.header.src + x_abort.bits.payload.client_xact_id := acquire.bits.payload.client_xact_id x_abort.valid := Bool(false) switch(abort_state) { is(s_idle) { when(want_to_abort) { - abort_state := Mux( co.messageHasData(x_init.bits.payload), s_abort_drain, s_abort_send) + abort_state := Mux( co.messageHasData(acquire.bits.payload), s_abort_drain, s_abort_send) } } - is(s_abort_drain) { // raises x_init_data.ready below - when(x_init_data.valid) { + is(s_abort_drain) { // raises acquire_data.ready below + when(acquire_data.valid) { abort_cnt := abort_cnt + UFix(1) when(abort_cnt === ~UFix(0, width = log2Up(REFILL_CYCLES))) { abort_state := s_abort_send @@ -603,38 +603,38 @@ class L2CoherenceAgent(implicit conf: CoherenceHubConfiguration) extends Coheren } is(s_abort_send) { // nothing is dequeued for now x_abort.valid := Bool(true) - when(x_abort.ready) { // raises x_init.ready + when(x_abort.ready) { // raises acquire.ready abort_state := s_idle } } } // Handle probe request generation - val p_req_arb = (new Arbiter(NGLOBAL_XACTS)){(new LogicalNetworkIO){ new Probe }} + val probe_arb = (new Arbiter(NGLOBAL_XACTS)){(new LogicalNetworkIO){ new Probe }} for( i <- 0 until NGLOBAL_XACTS ) { val t = trackerList(i).io - p_req_arb.io.in(i).bits := t.p_req.bits - p_req_arb.io.in(i).valid := t.p_req.valid - t.p_req.ready := p_req_arb.io.in(i).ready + probe_arb.io.in(i).bits := t.probe.bits + probe_arb.io.in(i).valid := t.probe.valid + t.probe.ready := probe_arb.io.in(i).ready } - io.network.probe <> p_req_arb.io.out + io.network.probe <> probe_arb.io.out // Handle probe replies, which may or may not have data - val p_rep = io.network.release - val p_rep_data = io.network.release_data - val idx = p_rep.bits.payload.master_xact_id - p_rep.ready := trackerList.map(_.io.p_rep.ready).reduce(_||_) - p_rep_data.ready := trackerList.map(_.io.p_rep_data.ready).reduce(_||_) - p_rep_data_dep_q.io.enq.valid := p_rep.valid && co.messageHasData(p_rep.bits.payload) - p_rep_data_dep_q.io.enq.bits.master_xact_id := p_rep.bits.payload.master_xact_id - p_rep_data_dep_q.io.deq.ready := trackerList.map(_.io.p_rep_data_dep.ready).reduce(_||_) + val release = io.network.release + val release_data = io.network.release_data + val idx = release.bits.payload.master_xact_id + release.ready := trackerList.map(_.io.release.ready).reduce(_||_) + release_data.ready := trackerList.map(_.io.release_data.ready).reduce(_||_) + release_data_dep_q.io.enq.valid := release.valid && co.messageHasData(release.bits.payload) + release_data_dep_q.io.enq.bits.master_xact_id := release.bits.payload.master_xact_id + release_data_dep_q.io.deq.ready := trackerList.map(_.io.release_data_dep.ready).reduce(_||_) for( i <- 0 until NGLOBAL_XACTS ) { - trackerList(i).io.p_rep_data.valid := p_rep_data.valid - trackerList(i).io.p_rep_data.bits := p_rep_data.bits - trackerList(i).io.p_rep_data_dep.valid := p_rep_data_dep_q.io.deq.valid - trackerList(i).io.p_rep_data_dep.bits := p_rep_data_dep_q.io.deq.bits - trackerList(i).io.p_rep.valid := p_rep.valid && (idx === UFix(i)) - trackerList(i).io.p_rep.bits := p_rep.bits + trackerList(i).io.release_data.valid := release_data.valid + trackerList(i).io.release_data.bits := release_data.bits + trackerList(i).io.release_data_dep.valid := release_data_dep_q.io.deq.valid + trackerList(i).io.release_data_dep.bits := release_data_dep_q.io.deq.bits + trackerList(i).io.release.valid := release.valid && (idx === UFix(i)) + trackerList(i).io.release.bits := release.bits } // Reply to initial requestor @@ -659,11 +659,11 @@ class L2CoherenceAgent(implicit conf: CoherenceHubConfiguration) extends Coheren } // Free finished transactions - val finish = io.network.grant_ack + val ack = io.network.grant_ack for( i <- 0 until NGLOBAL_XACTS ) { - trackerList(i).io.free := finish.valid && (finish.bits.payload.master_xact_id === UFix(i)) + trackerList(i).io.free := ack.valid && (ack.bits.payload.master_xact_id === UFix(i)) } - finish.ready := Bool(true) + ack.ready := Bool(true) // Create an arbiter for the one memory port // We have to arbitrate between the different trackers' memory requests @@ -683,20 +683,20 @@ class XactTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends Com val co = conf.co implicit val ln = conf.ln val io = new Bundle { - val x_init = (new FIFOIO){(new LogicalNetworkIO) { new Acquire }}.flip - val x_init_data = (new FIFOIO){(new LogicalNetworkIO) { new AcquireData }}.flip - val p_rep = (new FIFOIO){(new LogicalNetworkIO) { new Release }}.flip - val p_rep_data = (new FIFOIO){(new LogicalNetworkIO) { new ReleaseData }}.flip + val acquire = (new FIFOIO){(new LogicalNetworkIO) { new Acquire }}.flip + val acquire_data = (new FIFOIO){(new LogicalNetworkIO) { new AcquireData }}.flip + val release = (new FIFOIO){(new LogicalNetworkIO) { new Release }}.flip + val release_data = (new FIFOIO){(new LogicalNetworkIO) { new ReleaseData }}.flip val free = Bool(INPUT) val tile_incoherent = Bits(INPUT, conf.ln.nTiles) - val p_rep_data_dep = (new FIFOIO) { new TrackerDependency }.flip - val x_init_data_dep = (new FIFOIO) { new TrackerDependency }.flip + val release_data_dep = (new FIFOIO) { new TrackerDependency }.flip + val acquire_data_dep = (new FIFOIO) { new TrackerDependency }.flip val mem_resp = (new FIFOIO) { new MemResp }.flip val mem_req_cmd = (new FIFOIO) { new MemReqCmd } val mem_req_data = (new FIFOIO) { new MemData } val mem_req_lock = Bool(OUTPUT) - val p_req = (new FIFOIO) {(new LogicalNetworkIO) { new Probe }} + val probe = (new FIFOIO) {(new LogicalNetworkIO) { new Probe }} val grant = (new FIFOIO) {(new LogicalNetworkIO) { new Grant }} val busy = Bool(OUTPUT) val has_conflict = Bool(OUTPUT) @@ -708,32 +708,32 @@ class XactTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends Com val init_client_id_ = Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles))) //TODO: Will need id reg for merged release xacts val init_sharer_cnt_ = Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles))) - val p_rep_count = if (conf.ln.nTiles == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles))) - val p_req_flags = Reg(resetVal = Bits(0, width = conf.ln.nTiles)) + val release_count = if (conf.ln.nTiles == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles))) + val probe_flags = Reg(resetVal = Bits(0, width = conf.ln.nTiles)) val x_needs_read = Reg(resetVal = Bool(false)) - val x_init_data_needs_write = Reg(resetVal = Bool(false)) - val p_rep_data_needs_write = Reg(resetVal = Bool(false)) + val acquire_data_needs_write = Reg(resetVal = Bool(false)) + val release_data_needs_write = Reg(resetVal = Bool(false)) val x_w_mem_cmd_sent = Reg(resetVal = Bool(false)) val p_w_mem_cmd_sent = Reg(resetVal = Bool(false)) val mem_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES))) val mem_cnt_next = mem_cnt + UFix(1) val mem_cnt_max = ~UFix(0, width = log2Up(REFILL_CYCLES)) - val p_req_initial_flags = Bits(width = conf.ln.nTiles) - p_req_initial_flags := Bits(0) + val probe_initial_flags = Bits(width = conf.ln.nTiles) + probe_initial_flags := Bits(0) if (conf.ln.nTiles > 1) { // issue self-probes for uncached read xacts to facilitate I$ coherence // TODO: this is hackish; figure out how to do it more systematically val probe_self = co match { - case u: CoherencePolicyWithUncached => u.isUncachedReadTransaction(io.x_init.bits.payload) + case u: CoherencePolicyWithUncached => u.isUncachedReadTransaction(io.acquire.bits.payload) case _ => Bool(false) } - val myflag = Mux(probe_self, Bits(0), UFixToOH(io.x_init.bits.header.src(log2Up(conf.ln.nTiles)-1,0))) - p_req_initial_flags := ~(io.tile_incoherent | myflag) + val myflag = Mux(probe_self, Bits(0), UFixToOH(io.acquire.bits.header.src(log2Up(conf.ln.nTiles)-1,0))) + probe_initial_flags := ~(io.tile_incoherent | myflag) } val all_grants_require_acks = Bool(true) io.busy := state != s_idle - io.has_conflict := co.isCoherenceConflict(xact.addr, io.x_init.bits.payload.addr) && (state != s_idle) + io.has_conflict := co.isCoherenceConflict(xact.addr, io.acquire.bits.payload.addr) && (state != s_idle) io.mem_req_cmd.valid := Bool(false) io.mem_req_cmd.bits.rw := Bool(false) io.mem_req_cmd.bits.addr := xact.addr @@ -741,11 +741,11 @@ class XactTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends Com io.mem_req_data.valid := Bool(false) io.mem_req_data.bits.data := UFix(0) io.mem_req_lock := Bool(false) - io.p_req.valid := Bool(false) - io.p_req.bits.payload.p_type := co.getProbeType(xact.a_type, UFix(0)) - io.p_req.bits.payload.master_xact_id := UFix(id) - io.p_req.bits.payload.addr := xact.addr - io.p_req.bits.header.dst := UFix(0) + io.probe.valid := Bool(false) + io.probe.bits.payload.p_type := co.getProbeType(xact.a_type, UFix(0)) + io.probe.bits.payload.master_xact_id := UFix(id) + io.probe.bits.payload.addr := xact.addr + io.probe.bits.header.dst := UFix(0) io.grant.bits.payload.data := io.mem_resp.bits.data io.grant.bits.payload.g_type := co.getGrantType(xact.a_type, init_sharer_cnt_) io.grant.bits.payload.client_xact_id := xact.client_xact_id @@ -753,70 +753,70 @@ class XactTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends Com io.grant.bits.payload.require_ack := all_grants_require_acks io.grant.bits.header.dst := init_client_id_ io.grant.valid := (io.mem_resp.valid && (UFix(id) === io.mem_resp.bits.tag)) - io.x_init.ready := Bool(false) - io.x_init_data.ready := Bool(false) - io.x_init_data_dep.ready := Bool(false) - io.p_rep.ready := Bool(false) - io.p_rep_data.ready := Bool(false) - io.p_rep_data_dep.ready := Bool(false) + io.acquire.ready := Bool(false) + io.acquire_data.ready := Bool(false) + io.acquire_data_dep.ready := Bool(false) + io.release.ready := Bool(false) + io.release_data.ready := Bool(false) + io.release_data_dep.ready := Bool(false) io.mem_resp.ready := io.grant.ready switch (state) { is(s_idle) { - when( io.x_init.valid ) { - xact := io.x_init.bits.payload - init_client_id_ := io.x_init.bits.header.src + when( io.acquire.valid ) { + xact := io.acquire.bits.payload + init_client_id_ := io.acquire.bits.header.src init_sharer_cnt_ := UFix(conf.ln.nTiles) // TODO: Broadcast only - x_init_data_needs_write := co.messageHasData(io.x_init.bits.payload) - x_needs_read := co.needsMemRead(io.x_init.bits.payload.a_type, UFix(0)) - p_req_flags := p_req_initial_flags + acquire_data_needs_write := co.messageHasData(io.acquire.bits.payload) + x_needs_read := co.needsMemRead(io.acquire.bits.payload.a_type, UFix(0)) + probe_flags := probe_initial_flags mem_cnt := UFix(0) p_w_mem_cmd_sent := Bool(false) x_w_mem_cmd_sent := Bool(false) - io.x_init.ready := Bool(true) + io.acquire.ready := Bool(true) if(conf.ln.nTiles > 1) { - p_rep_count := PopCount(p_req_initial_flags) - state := Mux(p_req_initial_flags.orR, s_probe, s_mem) + release_count := PopCount(probe_initial_flags) + state := Mux(probe_initial_flags.orR, s_probe, s_mem) } else state := s_mem } } is(s_probe) { - val curr_p_id = PriorityEncoder(p_req_flags) - when(p_req_flags.orR) { - io.p_req.valid := Bool(true) - io.p_req.bits.header.dst := curr_p_id + val curr_p_id = PriorityEncoder(probe_flags) + when(probe_flags.orR) { + io.probe.valid := Bool(true) + io.probe.bits.header.dst := curr_p_id } - when(io.p_req.ready) { - p_req_flags := p_req_flags & ~(UFixToOH(curr_p_id)) + when(io.probe.ready) { + probe_flags := probe_flags & ~(UFixToOH(curr_p_id)) } - when(io.p_rep.valid) { - io.p_rep.ready := Bool(true) - if(conf.ln.nTiles > 1) p_rep_count := p_rep_count - UFix(1) - when(p_rep_count === UFix(1)) { + when(io.release.valid) { + io.release.ready := Bool(true) + if(conf.ln.nTiles > 1) release_count := release_count - UFix(1) + when(release_count === UFix(1)) { state := s_mem } - p_rep_data_needs_write := co.messageHasData(io.p_rep.bits.payload) + release_data_needs_write := co.messageHasData(io.release.bits.payload) } } is(s_mem) { - when (p_rep_data_needs_write) { + when (release_data_needs_write) { doMemReqWrite(io.mem_req_cmd, io.mem_req_data, io.mem_req_lock, - io.p_rep_data, - p_rep_data_needs_write, + io.release_data, + release_data_needs_write, p_w_mem_cmd_sent, - io.p_rep_data_dep.ready, - io.p_rep_data_dep.valid && (io.p_rep_data_dep.bits.master_xact_id === UFix(id))) - } . elsewhen(x_init_data_needs_write) { + io.release_data_dep.ready, + io.release_data_dep.valid && (io.release_data_dep.bits.master_xact_id === UFix(id))) + } . elsewhen(acquire_data_needs_write) { doMemReqWrite(io.mem_req_cmd, io.mem_req_data, io.mem_req_lock, - io.x_init_data, - x_init_data_needs_write, + io.acquire_data, + acquire_data_needs_write, x_w_mem_cmd_sent, - io.x_init_data_dep.ready, - io.x_init_data_dep.valid && (io.x_init_data_dep.bits.master_xact_id === UFix(id))) + io.acquire_data_dep.ready, + io.acquire_data_dep.valid && (io.acquire_data_dep.bits.master_xact_id === UFix(id))) } . elsewhen (x_needs_read) { doMemReqRead(io.mem_req_cmd, x_needs_read) } . otherwise { From 47a632cc59cb469458e1a6a8082ea4a0df64d403 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 28 Jan 2013 16:39:45 -0800 Subject: [PATCH 2/7] added support for voluntary wbs over the release network --- uncore/src/coherence.scala | 84 ++++++++++++++++++++--- uncore/src/package.scala | 15 ----- uncore/src/tilelink.scala | 15 ++++- uncore/src/uncore.scala | 135 ++++++++++++++++++++++++++++--------- 4 files changed, 189 insertions(+), 60 deletions(-) diff --git a/uncore/src/coherence.scala b/uncore/src/coherence.scala index 4268fcf8..e1cc453e 100644 --- a/uncore/src/coherence.scala +++ b/uncore/src/coherence.scala @@ -31,6 +31,7 @@ abstract class CoherencePolicy { def getAcquireTypeOnCacheControl(cmd: Bits): Bits def getAcquireTypeOnWriteback(): Bits + def getVoluntaryWriteback(addr: UFix, client_id: UFix, master_id: UFix): Release def newRelease (incoming: Probe, state: UFix): Release def messageHasData (reply: Release): Bool @@ -40,11 +41,15 @@ abstract class CoherencePolicy { def messageIsUncached(acq: Acquire): Bool def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool + def isVoluntary(rel: Release): Bool def getGrantType(a_type: UFix, count: UFix): Bits + def getGrantType(rel: Release, count: UFix): Bits def getProbeType(a_type: UFix, global_state: UFix): UFix def needsMemRead(a_type: UFix, global_state: UFix): Bool def needsMemWrite(a_type: UFix, global_state: UFix): Bool def needsAckReply(a_type: UFix, global_state: UFix): Bool + def requiresAck(grant: Grant): Bool + def requiresAck(release: Release): Bool } trait UncachedTransactions { @@ -70,17 +75,20 @@ abstract class IncoherentPolicy extends CoherencePolicy { def messageHasData (reply: Release) = Bool(false) def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool = Bool(false) def getGrantType(a_type: UFix, count: UFix): Bits = Bits(0) + def getGrantType(rel: Release, count: UFix): Bits = Bits(0) def getProbeType(a_type: UFix, global_state: UFix): UFix = UFix(0) def needsMemRead(a_type: UFix, global_state: UFix): Bool = Bool(false) def needsMemWrite(a_type: UFix, global_state: UFix): Bool = Bool(false) def needsAckReply(a_type: UFix, global_state: UFix): Bool = Bool(false) + def requiresAck(grant: Grant) = Bool(true) + def requiresAck(release: Release) = Bool(false) } class ThreeStateIncoherence extends IncoherentPolicy { val tileInvalid :: tileClean :: tileDirty :: Nil = Enum(3){ UFix() } val acquireReadClean :: acquireReadDirty :: acquireWriteback :: Nil = Enum(3){ UFix() } val grantData :: grantAck :: Nil = Enum(2){ UFix() } - val releaseInvalidateAck :: Nil = Enum(1){ UFix() } + val releaseVoluntaryInvalidateData :: releaseInvalidateAck :: Nil = Enum(2){ UFix() } val uncachedTypeList = List() val hasDataTypeList = List(acquireWriteback) @@ -106,6 +114,9 @@ class ThreeStateIncoherence extends IncoherentPolicy { )) } + def getVoluntaryWriteback(addr: UFix, client_id: UFix, master_id: UFix) = Release(releaseVoluntaryInvalidateData, addr, client_id, master_id) + def isVoluntary(rel: Release) = rel.r_type === releaseVoluntaryInvalidateData + def getAcquireTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = { val (read, write) = cpuCmdToRW(cmd) Mux(write || cmd === M_PFW, acquireReadDirty, acquireReadClean) @@ -129,9 +140,9 @@ class MICoherence extends CoherencePolicyWithUncached { val globalInvalid :: globalValid :: Nil = Enum(2){ UFix() } val acquireReadExclusive :: acquireReadUncached :: acquireWriteUncached :: acquireReadWordUncached :: acquireWriteWordUncached :: acquireAtomicUncached :: Nil = Enum(6){ UFix() } - val grantReadExclusive :: grantReadUncached :: grantWriteUncached :: grantReadWordUncached :: grantWriteWordUncached :: grantAtomicUncached :: Nil = Enum(6){ UFix() } + val grantVoluntaryAck :: grantReadExclusive :: grantReadUncached :: grantWriteUncached :: grantReadWordUncached :: grantWriteWordUncached :: grantAtomicUncached :: Nil = Enum(7){ UFix() } val probeInvalidate :: probeCopy :: Nil = Enum(2){ UFix() } - val releaseInvalidateData :: releaseCopyData :: releaseInvalidateAck :: releaseCopyAck :: Nil = Enum(4){ UFix() } + val releaseVoluntaryInvalidateData :: releaseInvalidateData :: releaseCopyData :: releaseInvalidateAck :: releaseCopyAck :: Nil = Enum(5){ UFix() } val uncachedTypeList = List(acquireReadUncached, acquireWriteUncached, grantReadWordUncached, acquireWriteWordUncached, acquireAtomicUncached) val hasDataTypeList = List(acquireWriteUncached, acquireWriteWordUncached, acquireAtomicUncached) @@ -180,7 +191,9 @@ class MICoherence extends CoherencePolicyWithUncached { def getUncachedReadWordAcquire(addr: UFix, id: UFix) = Acquire(acquireReadWordUncached, addr, id) def getUncachedWriteWordAcquire(addr: UFix, id: UFix, write_mask: Bits) = Acquire(acquireWriteWordUncached, addr, id, write_mask) def getUncachedAtomicAcquire(addr: UFix, id: UFix, subword_addr: UFix, atomic_op: UFix) = Acquire(acquireAtomicUncached, addr, id, subword_addr, atomic_op) + def getVoluntaryWriteback(addr: UFix, client_id: UFix, master_id: UFix) = Release(releaseVoluntaryInvalidateData, addr, client_id, master_id) def isUncachedReadTransaction(acq: Acquire) = acq.a_type === acquireReadUncached + def isVoluntary(rel: Release) = rel.r_type === releaseVoluntaryInvalidateData def getAcquireTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = acquireReadExclusive def getAcquireTypeOnSecondaryMiss(cmd: Bits, state: UFix, outstanding: Acquire): UFix = acquireReadExclusive @@ -228,6 +241,12 @@ class MICoherence extends CoherencePolicyWithUncached { )) } + def getGrantType(rel: Release, count: UFix): Bits = { + MuxLookup(rel.r_type, grantReadUncached, Array( + releaseVoluntaryInvalidateData -> grantVoluntaryAck + )) + } + def getProbeType(a_type: UFix, global_state: UFix): UFix = { MuxLookup(a_type, probeCopy, Array( acquireReadExclusive -> probeInvalidate, @@ -248,6 +267,8 @@ class MICoherence extends CoherencePolicyWithUncached { def needsAckReply(a_type: UFix, global_state: UFix): Bool = { (a_type === acquireWriteUncached) } + def requiresAck(grant: Grant) = Bool(true) + def requiresAck(release: Release) = Bool(false) } class MEICoherence extends CoherencePolicyWithUncached { @@ -256,9 +277,9 @@ class MEICoherence extends CoherencePolicyWithUncached { val globalInvalid :: globalExclusiveClean :: Nil = Enum(2){ UFix() } val acquireReadExclusiveClean :: acquireReadExclusiveDirty :: acquireReadUncached :: acquireWriteUncached :: acquireReadWordUncached :: acquireWriteWordUncached :: acquireAtomicUncached :: Nil = Enum(7){ UFix() } - val grantReadExclusive :: grantReadUncached :: grantWriteUncached :: grantReadExclusiveAck :: grantReadWordUncached :: grantWriteWordUncached :: grantAtomicUncached :: Nil = Enum(7){ UFix() } + val grantVoluntaryAck :: grantReadExclusive :: grantReadUncached :: grantWriteUncached :: grantReadExclusiveAck :: grantReadWordUncached :: grantWriteWordUncached :: grantAtomicUncached :: Nil = Enum(8){ UFix() } val probeInvalidate :: probeDowngrade :: probeCopy :: Nil = Enum(3){ UFix() } - val releaseInvalidateData :: releaseDowngradeData :: releaseCopyData :: releaseInvalidateAck :: releaseDowngradeAck :: releaseCopyAck :: Nil = Enum(6){ UFix() } + val releaseVoluntaryInvalidateData :: releaseInvalidateData :: releaseDowngradeData :: releaseCopyData :: releaseInvalidateAck :: releaseDowngradeAck :: releaseCopyAck :: Nil = Enum(7){ UFix() } val uncachedTypeList = List(acquireReadUncached, acquireWriteUncached, grantReadWordUncached, acquireWriteWordUncached, acquireAtomicUncached) val hasDataTypeList = List(acquireWriteUncached, acquireWriteWordUncached, acquireAtomicUncached) @@ -316,7 +337,9 @@ class MEICoherence extends CoherencePolicyWithUncached { def getUncachedReadWordAcquire(addr: UFix, id: UFix) = Acquire(acquireReadWordUncached, addr, id) def getUncachedWriteWordAcquire(addr: UFix, id: UFix, write_mask: Bits) = Acquire(acquireWriteWordUncached, addr, id, write_mask) def getUncachedAtomicAcquire(addr: UFix, id: UFix, subword_addr: UFix, atomic_op: UFix) = Acquire(acquireAtomicUncached, addr, id, subword_addr, atomic_op) + def getVoluntaryWriteback(addr: UFix, client_id: UFix, master_id: UFix) = Release(releaseVoluntaryInvalidateData, addr, client_id, master_id) def isUncachedReadTransaction(acq: Acquire) = acq.a_type === acquireReadUncached + def isVoluntary(rel: Release) = rel.r_type === releaseVoluntaryInvalidateData def getAcquireTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = { val (read, write) = cpuCmdToRW(cmd) @@ -373,6 +396,12 @@ class MEICoherence extends CoherencePolicyWithUncached { acquireAtomicUncached -> grantAtomicUncached )) } + def getGrantType(rel: Release, count: UFix): Bits = { + MuxLookup(rel.r_type, grantReadUncached, Array( + releaseVoluntaryInvalidateData -> grantVoluntaryAck + )) + } + def getProbeType(a_type: UFix, global_state: UFix): UFix = { MuxLookup(a_type, probeCopy, Array( @@ -395,6 +424,8 @@ class MEICoherence extends CoherencePolicyWithUncached { def needsAckReply(a_type: UFix, global_state: UFix): Bool = { (a_type === acquireWriteUncached) } + def requiresAck(grant: Grant) = Bool(true) + def requiresAck(release: Release) = Bool(false) } class MSICoherence extends CoherencePolicyWithUncached { @@ -403,9 +434,9 @@ class MSICoherence extends CoherencePolicyWithUncached { val globalInvalid :: globalShared :: globalExclusive :: Nil = Enum(3){ UFix() } val acquireReadShared :: acquireReadExclusive :: acquireReadUncached :: acquireWriteUncached :: acquireReadWordUncached :: acquireWriteWordUncached :: acquireAtomicUncached :: Nil = Enum(7){ UFix() } - val grantReadShared :: grantReadExclusive :: grantReadUncached :: grantWriteUncached :: grantReadExclusiveAck :: grantReadWordUncached :: grantWriteWordUncached :: grantAtomicUncached :: Nil = Enum(8){ UFix() } + val grantVoluntaryAck :: grantReadShared :: grantReadExclusive :: grantReadUncached :: grantWriteUncached :: grantReadExclusiveAck :: grantReadWordUncached :: grantWriteWordUncached :: grantAtomicUncached :: Nil = Enum(9){ UFix() } val probeInvalidate :: probeDowngrade :: probeCopy :: Nil = Enum(3){ UFix() } - val releaseInvalidateData :: releaseDowngradeData :: releaseCopyData :: releaseInvalidateAck :: releaseDowngradeAck :: releaseCopyAck :: Nil = Enum(6){ UFix() } + val releaseVoluntaryInvalidateData :: releaseInvalidateData :: releaseDowngradeData :: releaseCopyData :: releaseInvalidateAck :: releaseDowngradeAck :: releaseCopyAck :: Nil = Enum(7){ UFix() } val uncachedTypeList = List(acquireReadUncached, acquireWriteUncached, grantReadWordUncached, acquireWriteWordUncached, acquireAtomicUncached) val hasDataTypeList = List(acquireWriteUncached, acquireWriteWordUncached, acquireAtomicUncached) @@ -470,7 +501,9 @@ class MSICoherence extends CoherencePolicyWithUncached { def getUncachedReadWordAcquire(addr: UFix, id: UFix) = Acquire(acquireReadWordUncached, addr, id) def getUncachedWriteWordAcquire(addr: UFix, id: UFix, write_mask: Bits) = Acquire(acquireWriteWordUncached, addr, id, write_mask) def getUncachedAtomicAcquire(addr: UFix, id: UFix, subword_addr: UFix, atomic_op: UFix) = Acquire(acquireAtomicUncached, addr, id, subword_addr, atomic_op) + def getVoluntaryWriteback(addr: UFix, client_id: UFix, master_id: UFix) = Release(releaseVoluntaryInvalidateData, addr, client_id, master_id) def isUncachedReadTransaction(acq: Acquire) = acq.a_type === acquireReadUncached + def isVoluntary(rel: Release) = rel.r_type === releaseVoluntaryInvalidateData def getAcquireTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = { val (read, write) = cpuCmdToRW(cmd) @@ -527,6 +560,12 @@ class MSICoherence extends CoherencePolicyWithUncached { acquireAtomicUncached -> grantAtomicUncached )) } + def getGrantType(rel: Release, count: UFix): Bits = { + MuxLookup(rel.r_type, grantReadUncached, Array( + releaseVoluntaryInvalidateData -> grantVoluntaryAck + )) + } + def getProbeType(a_type: UFix, global_state: UFix): UFix = { MuxLookup(a_type, probeCopy, Array( @@ -546,6 +585,8 @@ class MSICoherence extends CoherencePolicyWithUncached { def needsAckReply(a_type: UFix, global_state: UFix): Bool = { (a_type === acquireWriteUncached) } + def requiresAck(grant: Grant) = Bool(true) + def requiresAck(release: Release) = Bool(false) } class MESICoherence extends CoherencePolicyWithUncached { @@ -554,9 +595,9 @@ class MESICoherence extends CoherencePolicyWithUncached { val globalInvalid :: globalShared :: globalExclusiveClean :: Nil = Enum(3){ UFix() } val acquireReadShared :: acquireReadExclusive :: acquireReadUncached :: acquireWriteUncached :: acquireReadWordUncached :: acquireWriteWordUncached :: acquireAtomicUncached :: Nil = Enum(7){ UFix() } - val grantReadShared :: grantReadExclusive :: grantReadUncached :: grantWriteUncached :: grantReadExclusiveAck :: grantReadWordUncached :: grantWriteWordUncached :: grantAtomicUncached :: Nil = Enum(8){ UFix() } + val grantVoluntaryAck :: grantReadShared :: grantReadExclusive :: grantReadUncached :: grantWriteUncached :: grantReadExclusiveAck :: grantReadWordUncached :: grantWriteWordUncached :: grantAtomicUncached :: Nil = Enum(9){ UFix() } val probeInvalidate :: probeDowngrade :: probeCopy :: Nil = Enum(3){ UFix() } - val releaseInvalidateData :: releaseDowngradeData :: releaseCopyData :: releaseInvalidateAck :: releaseDowngradeAck :: releaseCopyAck :: Nil = Enum(6){ UFix() } + val releaseVoluntaryInvalidateData :: releaseInvalidateData :: releaseDowngradeData :: releaseCopyData :: releaseInvalidateAck :: releaseDowngradeAck :: releaseCopyAck :: Nil = Enum(7){ UFix() } val uncachedTypeList = List(acquireReadUncached, acquireWriteUncached, acquireReadWordUncached, acquireWriteWordUncached, acquireAtomicUncached) val hasDataTypeList = List(acquireWriteUncached, acquireWriteWordUncached, acquireAtomicUncached) @@ -621,7 +662,9 @@ class MESICoherence extends CoherencePolicyWithUncached { def getUncachedReadWordAcquire(addr: UFix, id: UFix) = Acquire(acquireReadWordUncached, addr, id) def getUncachedWriteWordAcquire(addr: UFix, id: UFix, write_mask: Bits) = Acquire(acquireWriteWordUncached, addr, id, write_mask) def getUncachedAtomicAcquire(addr: UFix, id: UFix, subword_addr: UFix, atomic_op: UFix) = Acquire(acquireAtomicUncached, addr, id, subword_addr, atomic_op) + def getVoluntaryWriteback(addr: UFix, client_id: UFix, master_id: UFix) = Release(releaseVoluntaryInvalidateData, addr, client_id, master_id) def isUncachedReadTransaction(acq: Acquire) = acq.a_type === acquireReadUncached + def isVoluntary(rel: Release) = rel.r_type === releaseVoluntaryInvalidateData def getAcquireTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = { val (read, write) = cpuCmdToRW(cmd) @@ -678,6 +721,12 @@ class MESICoherence extends CoherencePolicyWithUncached { acquireAtomicUncached -> grantAtomicUncached )) } + def getGrantType(rel: Release, count: UFix): Bits = { + MuxLookup(rel.r_type, grantReadUncached, Array( + releaseVoluntaryInvalidateData -> grantVoluntaryAck + )) + } + def getProbeType(a_type: UFix, global_state: UFix): UFix = { MuxLookup(a_type, probeCopy, Array( @@ -700,6 +749,9 @@ class MESICoherence extends CoherencePolicyWithUncached { def needsAckReply(a_type: UFix, global_state: UFix): Bool = { (a_type === acquireWriteUncached) } + + def requiresAck(grant: Grant) = Bool(true) + def requiresAck(release: Release) = Bool(false) } class MigratoryCoherence extends CoherencePolicyWithUncached { @@ -707,9 +759,9 @@ class MigratoryCoherence extends CoherencePolicyWithUncached { val tileInvalid :: tileShared :: tileExclusiveClean :: tileExclusiveDirty :: tileSharedByTwo :: tileMigratoryClean :: tileMigratoryDirty :: Nil = Enum(7){ UFix() } val acquireReadShared :: acquireReadExclusive :: acquireReadUncached :: acquireWriteUncached :: acquireReadWordUncached :: acquireWriteWordUncached :: acquireAtomicUncached :: acquireInvalidateOthers :: Nil = Enum(8){ UFix() } - val grantReadShared :: grantReadExclusive :: grantReadUncached :: grantWriteUncached :: grantReadExclusiveAck :: grantReadWordUncached :: grantWriteWordUncached :: grantAtomicUncached :: grantReadMigratory :: Nil = Enum(9){ UFix() } + val grantVoluntaryAck :: grantReadShared :: grantReadExclusive :: grantReadUncached :: grantWriteUncached :: grantReadExclusiveAck :: grantReadWordUncached :: grantWriteWordUncached :: grantAtomicUncached :: grantReadMigratory :: Nil = Enum(10){ UFix() } val probeInvalidate :: probeDowngrade :: probeCopy :: probeInvalidateOthers :: Nil = Enum(4){ UFix() } - val releaseInvalidateData :: releaseDowngradeData :: releaseCopyData :: releaseInvalidateAck :: releaseDowngradeAck :: releaseCopyAck :: releaseDowngradeDataMigratory :: releaseDowngradeAckHasCopy :: releaseInvalidateDataMigratory :: releaseInvalidateAckMigratory :: Nil = Enum(10){ UFix() } + val releaseVoluntaryInvalidateData :: releaseInvalidateData :: releaseDowngradeData :: releaseCopyData :: releaseInvalidateAck :: releaseDowngradeAck :: releaseCopyAck :: releaseDowngradeDataMigratory :: releaseDowngradeAckHasCopy :: releaseInvalidateDataMigratory :: releaseInvalidateAckMigratory :: Nil = Enum(11){ UFix() } val uncachedTypeList = List(acquireReadUncached, acquireWriteUncached, acquireReadWordUncached, acquireWriteWordUncached, acquireAtomicUncached) val hasDataTypeList = List(acquireWriteUncached, acquireWriteWordUncached, acquireAtomicUncached) @@ -789,7 +841,9 @@ class MigratoryCoherence extends CoherencePolicyWithUncached { def getUncachedReadWordAcquire(addr: UFix, id: UFix) = Acquire(acquireReadWordUncached, addr, id) def getUncachedWriteWordAcquire(addr: UFix, id: UFix, write_mask: Bits) = Acquire(acquireWriteWordUncached, addr, id, write_mask) def getUncachedAtomicAcquire(addr: UFix, id: UFix, subword_addr: UFix, atomic_op: UFix) = Acquire(acquireAtomicUncached, addr, id, subword_addr, atomic_op) + def getVoluntaryWriteback(addr: UFix, client_id: UFix, master_id: UFix) = Release(releaseVoluntaryInvalidateData, addr, client_id, master_id) def isUncachedReadTransaction(acq: Acquire) = acq.a_type === acquireReadUncached + def isVoluntary(rel: Release) = rel.r_type === releaseVoluntaryInvalidateData def getAcquireTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = { val (read, write) = cpuCmdToRW(cmd) @@ -848,6 +902,12 @@ class MigratoryCoherence extends CoherencePolicyWithUncached { acquireInvalidateOthers -> grantReadExclusiveAck //TODO: add this to MESI? )) } + def getGrantType(rel: Release, count: UFix): Bits = { + MuxLookup(rel.r_type, grantReadUncached, Array( + releaseVoluntaryInvalidateData -> grantVoluntaryAck + )) + } + def getProbeType(a_type: UFix, global_state: UFix): UFix = { MuxLookup(a_type, probeCopy, Array( @@ -871,4 +931,6 @@ class MigratoryCoherence extends CoherencePolicyWithUncached { def needsAckReply(a_type: UFix, global_state: UFix): Bool = { (a_type === acquireWriteUncached || a_type === acquireWriteWordUncached ||a_type === acquireInvalidateOthers) } + def requiresAck(grant: Grant) = Bool(true) + def requiresAck(release: Release) = Bool(false) } diff --git a/uncore/src/package.scala b/uncore/src/package.scala index 0e69ff47..8e511663 100644 --- a/uncore/src/package.scala +++ b/uncore/src/package.scala @@ -105,19 +105,4 @@ class LogicalNetworkIO[T <: Data]()(data: => T)(implicit conf: LogicalNetworkCon override def clone = { new LogicalNetworkIO()(data).asInstanceOf[this.type] } } -abstract class DirectionalFIFOIO[T <: Data]()(data: => T) extends FIFOIO()(data) -class ClientSourcedIO[T <: Data]()(data: => T) extends DirectionalFIFOIO()(data) -class MasterSourcedIO[T <: Data]()(data: => T) extends DirectionalFIFOIO()(data) {flip()} - -class TileLinkIO(implicit conf: LogicalNetworkConfiguration) extends Bundle { - val acquire = (new ClientSourcedIO){(new LogicalNetworkIO){new Acquire }} - val acquire_data = (new ClientSourcedIO){(new LogicalNetworkIO){new AcquireData }} - val abort = (new MasterSourcedIO){(new LogicalNetworkIO){new Abort }} - val probe = (new MasterSourcedIO){(new LogicalNetworkIO){new Probe }} - val release = (new ClientSourcedIO){(new LogicalNetworkIO){new Release }} - val release_data = (new ClientSourcedIO){(new LogicalNetworkIO){new ReleaseData }} - val grant = (new MasterSourcedIO){(new LogicalNetworkIO){new Grant }} - val grant_ack = (new ClientSourcedIO){(new LogicalNetworkIO){new GrantAck }} - override def clone = { new TileLinkIO().asInstanceOf[this.type] } -} } diff --git a/uncore/src/tilelink.scala b/uncore/src/tilelink.scala index 8ff26adc..51b64b16 100644 --- a/uncore/src/tilelink.scala +++ b/uncore/src/tilelink.scala @@ -79,8 +79,20 @@ class Probe extends PhysicalAddress { val master_xact_id = Bits(width = MASTER_XACT_ID_BITS) } -class Release extends Bundle { +object Release +{ + def apply(r_type: Bits, addr: UFix, client_xact_id: UFix, master_xact_id: UFix) = { + val rel = new Release + rel.r_type := r_type + rel.addr := addr + rel.client_xact_id := client_xact_id + rel.master_xact_id := master_xact_id + rel + } +} +class Release extends PhysicalAddress { val r_type = Bits(width = RELEASE_TYPE_MAX_BITS) + val client_xact_id = Bits(width = CLIENT_XACT_ID_BITS) val master_xact_id = Bits(width = MASTER_XACT_ID_BITS) } @@ -90,7 +102,6 @@ class Grant extends MemData { val g_type = Bits(width = GRANT_TYPE_MAX_BITS) val client_xact_id = Bits(width = CLIENT_XACT_ID_BITS) val master_xact_id = Bits(width = MASTER_XACT_ID_BITS) - val require_ack = Bool() } class GrantAck extends Bundle { diff --git a/uncore/src/uncore.scala b/uncore/src/uncore.scala index 21aaba8c..a439c7b6 100644 --- a/uncore/src/uncore.scala +++ b/uncore/src/uncore.scala @@ -288,7 +288,6 @@ class CoherenceHubNull(implicit conf: CoherenceHubConfiguration) extends Coheren grant.bits.payload.client_xact_id := Mux(io.mem.resp.valid, io.mem.resp.bits.tag, acquire.bits.payload.client_xact_id) grant.bits.payload.master_xact_id := UFix(0) // don't care grant.bits.payload.data := io.mem.resp.bits.data - grant.bits.payload.require_ack := Bool(true) grant.valid := io.mem.resp.valid || acquire.valid && is_write && io.mem.req_cmd.ready io.tiles(0).abort.valid := Bool(false) @@ -368,7 +367,6 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co rep.bits.payload.client_xact_id := UFix(0) rep.bits.payload.master_xact_id := UFix(0) rep.bits.payload.data := io.mem.resp.bits.data - rep.bits.payload.require_ack := Bool(true) rep.valid := Bool(false) when(io.mem.resp.valid && (UFix(j) === init_client_id_arr(mem_idx))) { rep.bits.payload.g_type := co.getGrantType(a_type_arr(mem_idx), sh_count_arr(mem_idx)) @@ -537,11 +535,11 @@ class L2CoherenceAgent(implicit conf: CoherenceHubConfiguration) extends Coheren { implicit val lnConf = conf.ln val co = conf.co - val trackerList = (0 until NGLOBAL_XACTS).map(new XactTracker(_)) + val trackerList = new WritebackTracker(0) +: (1 to NGLOBAL_XACTS).map(new AcquireTracker(_)) val release_data_dep_q = (new Queue(NGLOBAL_XACTS)){new TrackerDependency} // depth must >= NPRIMARY val acquire_data_dep_q = (new Queue(NGLOBAL_XACTS)){new TrackerDependency} // depth should >= NPRIMARY - for( i <- 0 until NGLOBAL_XACTS ) { + for( i <- 0 to NGLOBAL_XACTS ) { val t = trackerList(i) t.io.tile_incoherent := io.incoherent.toBits t.io.mem_resp.valid := io.mem.resp.valid && (io.mem.resp.bits.tag === UFix(i)) @@ -559,12 +557,12 @@ class L2CoherenceAgent(implicit conf: CoherenceHubConfiguration) extends Coheren val s_idle :: s_abort_drain :: s_abort_send :: Nil = Enum(3){ UFix() } val abort_state = Reg(resetVal = s_idle) val abort_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES))) - val any_conflict = trackerList.map(_.io.has_conflict).reduce(_||_) + val any_acquire_conflict = trackerList.map(_.io.has_acquire_conflict).reduce(_||_) val all_busy = trackerList.map(_.io.busy).reduce(_&&_) - val want_to_abort = acquire.valid && (any_conflict || all_busy || (!acquire_data_dep_q.io.enq.ready && co.messageHasData(acquire.bits.payload))) + val want_to_abort = acquire.valid && (any_acquire_conflict || all_busy || (!acquire_data_dep_q.io.enq.ready && co.messageHasData(acquire.bits.payload))) - val alloc_arb = (new Arbiter(NGLOBAL_XACTS)) { Bool() } - for( i <- 0 until NGLOBAL_XACTS ) { + val alloc_arb = (new Arbiter(NGLOBAL_XACTS+1)) { Bool() } + for( i <- 0 to NGLOBAL_XACTS ) { alloc_arb.io.in(i).valid := !trackerList(i).io.busy trackerList(i).io.acquire.bits := acquire.bits trackerList(i).io.acquire.valid := (abort_state === s_idle) && !want_to_abort && acquire.valid && alloc_arb.io.in(i).ready @@ -610,8 +608,8 @@ class L2CoherenceAgent(implicit conf: CoherenceHubConfiguration) extends Coheren } // Handle probe request generation - val probe_arb = (new Arbiter(NGLOBAL_XACTS)){(new LogicalNetworkIO){ new Probe }} - for( i <- 0 until NGLOBAL_XACTS ) { + val probe_arb = (new Arbiter(NGLOBAL_XACTS+1)){(new LogicalNetworkIO){ new Probe }} + for( i <- 0 to NGLOBAL_XACTS ) { val t = trackerList(i).io probe_arb.io.in(i).bits := t.probe.bits probe_arb.io.in(i).valid := t.probe.valid @@ -622,13 +620,16 @@ class L2CoherenceAgent(implicit conf: CoherenceHubConfiguration) extends Coheren // Handle probe replies, which may or may not have data val release = io.network.release val release_data = io.network.release_data - val idx = release.bits.payload.master_xact_id + val voluntary = co.isVoluntary(release.bits.payload) + val any_release_conflict = trackerList.tail.map(_.io.has_release_conflict).reduce(_||_) + val conflict_idx = Vec(trackerList.map(_.io.has_release_conflict)){Bool()}.lastIndexWhere{b: Bool => b} + val idx = Mux(voluntary, Mux(any_release_conflict, conflict_idx, UFix(0)), release.bits.payload.master_xact_id) release.ready := trackerList.map(_.io.release.ready).reduce(_||_) release_data.ready := trackerList.map(_.io.release_data.ready).reduce(_||_) release_data_dep_q.io.enq.valid := release.valid && co.messageHasData(release.bits.payload) - release_data_dep_q.io.enq.bits.master_xact_id := release.bits.payload.master_xact_id + release_data_dep_q.io.enq.bits.master_xact_id := idx release_data_dep_q.io.deq.ready := trackerList.map(_.io.release_data_dep.ready).reduce(_||_) - for( i <- 0 until NGLOBAL_XACTS ) { + for( i <- 0 to NGLOBAL_XACTS ) { trackerList(i).io.release_data.valid := release_data.valid trackerList(i).io.release_data.bits := release_data.bits trackerList(i).io.release_data_dep.valid := release_data_dep_q.io.deq.valid @@ -639,28 +640,27 @@ class L2CoherenceAgent(implicit conf: CoherenceHubConfiguration) extends Coheren // Reply to initial requestor // Forward memory responses from mem to tile or arbitrate to ack - val grant_arb = (new Arbiter(NGLOBAL_XACTS)){(new LogicalNetworkIO){ new Grant }} - for( i <- 0 until NGLOBAL_XACTS ) { + val grant_arb = (new Arbiter(NGLOBAL_XACTS+1)){(new LogicalNetworkIO){ new Grant }} + for( i <- 0 to NGLOBAL_XACTS ) { val t = trackerList(i).io grant_arb.io.in(i).bits := t.grant.bits grant_arb.io.in(i).valid := t.grant.valid t.grant.ready := grant_arb.io.in(i).ready } - grant_arb.io.out.ready := Bool(false) io.network.grant.valid := grant_arb.io.out.valid io.network.grant.bits := grant_arb.io.out.bits grant_arb.io.out.ready := io.network.grant.ready when(io.mem.resp.valid) { io.network.grant.valid := Bool(true) io.network.grant.bits := Vec(trackerList.map(_.io.grant.bits)){(new LogicalNetworkIO){new Grant}}(io.mem.resp.bits.tag) - for( i <- 0 until NGLOBAL_XACTS ) { + for( i <- 0 to NGLOBAL_XACTS ) { trackerList(i).io.grant.ready := (io.mem.resp.bits.tag === UFix(i)) && io.network.grant.ready } } // Free finished transactions val ack = io.network.grant_ack - for( i <- 0 until NGLOBAL_XACTS ) { + for( i <- 0 to NGLOBAL_XACTS ) { trackerList(i).io.free := ack.valid && (ack.bits.payload.master_xact_id === UFix(i)) } ack.ready := Bool(true) @@ -668,9 +668,9 @@ class L2CoherenceAgent(implicit conf: CoherenceHubConfiguration) extends Coheren // Create an arbiter for the one memory port // We have to arbitrate between the different trackers' memory requests // and once we have picked a request, get the right write data - val mem_req_cmd_arb = (new Arbiter(NGLOBAL_XACTS)) { new MemReqCmd() } - val mem_req_data_arb = (new LockingArbiter(NGLOBAL_XACTS)) { new MemData() } - for( i <- 0 until NGLOBAL_XACTS ) { + val mem_req_cmd_arb = (new Arbiter(NGLOBAL_XACTS+1)) { new MemReqCmd() } + val mem_req_data_arb = (new LockingArbiter(NGLOBAL_XACTS+1)) { new MemData() } + for( i <- 0 to NGLOBAL_XACTS ) { mem_req_cmd_arb.io.in(i) <> trackerList(i).io.mem_req_cmd mem_req_data_arb.io.in(i) <> trackerList(i).io.mem_req_data mem_req_data_arb.io.lock(i) <> trackerList(i).io.mem_req_lock @@ -679,7 +679,8 @@ class L2CoherenceAgent(implicit conf: CoherenceHubConfiguration) extends Coheren io.mem.req_data <> Queue(mem_req_data_arb.io.out) } -class XactTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends Component { + +abstract class XactTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends Component with MemoryRequestGenerator { val co = conf.co implicit val ln = conf.ln val io = new Bundle { @@ -699,15 +700,83 @@ class XactTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends Com val probe = (new FIFOIO) {(new LogicalNetworkIO) { new Probe }} val grant = (new FIFOIO) {(new LogicalNetworkIO) { new Grant }} val busy = Bool(OUTPUT) - val has_conflict = Bool(OUTPUT) + val has_acquire_conflict = Bool(OUTPUT) + val has_release_conflict = Bool(OUTPUT) } +} +class WritebackTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends XactTracker(id)(conf) { + val s_idle :: s_mem :: s_ack :: s_busy :: Nil = Enum(4){ UFix() } + val state = Reg(resetVal = s_idle) + val xact = Reg{ new Release } + val init_client_id_ = Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles))) + val release_data_needs_write = Reg(resetVal = Bool(false)) + val mem_cmd_sent = Reg(resetVal = Bool(false)) + + io.acquire.ready := Bool(false) + io.acquire_data.ready := Bool(false) + io.acquire_data_dep.ready := Bool(false) + io.mem_resp.ready := Bool(false) + io.probe.valid := Bool(false) + io.busy := Bool(true) + io.has_acquire_conflict := Bool(false) + io.has_release_conflict := co.isCoherenceConflict(xact.addr, io.release.bits.payload.addr) && (state != s_idle) + + io.mem_req_cmd.valid := Bool(false) + io.mem_req_cmd.bits.rw := Bool(false) + io.mem_req_cmd.bits.addr := xact.addr + io.mem_req_cmd.bits.tag := UFix(id) + io.mem_req_data.valid := Bool(false) + io.mem_req_data.bits.data := UFix(0) + io.mem_req_lock := Bool(false) + io.release.ready := Bool(false) + io.release_data.ready := Bool(false) + io.release_data_dep.ready := Bool(false) + io.grant.valid := Bool(false) + io.grant.bits.payload.g_type := co.getGrantType(xact, UFix(0)) + io.grant.bits.payload.client_xact_id := xact.client_xact_id + io.grant.bits.payload.master_xact_id := UFix(id) + io.grant.bits.header.dst := init_client_id_ + + switch (state) { + is(s_idle) { + when( io.release.valid ) { + xact := io.release.bits.payload + init_client_id_ := io.release.bits.header.src + release_data_needs_write := co.messageHasData(io.release.bits.payload) + mem_cnt := UFix(0) + mem_cmd_sent := Bool(false) + io.release.ready := Bool(true) + state := s_mem + } + } + is(s_mem) { + when (release_data_needs_write) { + doMemReqWrite(io.mem_req_cmd, + io.mem_req_data, + io.mem_req_lock, + io.release_data, + release_data_needs_write, + mem_cmd_sent, + io.release_data_dep.ready, + io.release_data_dep.valid && (io.release_data_dep.bits.master_xact_id === UFix(id))) + } . otherwise { state := s_ack } + } + is(s_ack) { + io.grant.valid := Bool(true) + when(io.grant.ready) { state := s_idle } + } + } +} + +class AcquireTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends XactTracker(id)(conf) { val s_idle :: s_ack :: s_mem :: s_probe :: s_busy :: Nil = Enum(5){ UFix() } val state = Reg(resetVal = s_idle) val xact = Reg{ new Acquire } val init_client_id_ = Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles))) //TODO: Will need id reg for merged release xacts val init_sharer_cnt_ = Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles))) + val grant_type = co.getGrantType(xact.a_type, init_sharer_cnt_) val release_count = if (conf.ln.nTiles == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles))) val probe_flags = Reg(resetVal = Bits(0, width = conf.ln.nTiles)) val x_needs_read = Reg(resetVal = Bool(false)) @@ -715,9 +784,6 @@ class XactTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends Com val release_data_needs_write = Reg(resetVal = Bool(false)) val x_w_mem_cmd_sent = Reg(resetVal = Bool(false)) val p_w_mem_cmd_sent = Reg(resetVal = Bool(false)) - val mem_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES))) - val mem_cnt_next = mem_cnt + UFix(1) - val mem_cnt_max = ~UFix(0, width = log2Up(REFILL_CYCLES)) val probe_initial_flags = Bits(width = conf.ln.nTiles) probe_initial_flags := Bits(0) if (conf.ln.nTiles > 1) { @@ -730,10 +796,10 @@ class XactTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends Com val myflag = Mux(probe_self, Bits(0), UFixToOH(io.acquire.bits.header.src(log2Up(conf.ln.nTiles)-1,0))) probe_initial_flags := ~(io.tile_incoherent | myflag) } - val all_grants_require_acks = Bool(true) io.busy := state != s_idle - io.has_conflict := co.isCoherenceConflict(xact.addr, io.acquire.bits.payload.addr) && (state != s_idle) + io.has_acquire_conflict := co.isCoherenceConflict(xact.addr, io.acquire.bits.payload.addr) && (state != s_idle) + io.has_release_conflict := co.isCoherenceConflict(xact.addr, io.release.bits.payload.addr) && (state != s_idle) io.mem_req_cmd.valid := Bool(false) io.mem_req_cmd.bits.rw := Bool(false) io.mem_req_cmd.bits.addr := xact.addr @@ -747,10 +813,9 @@ class XactTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends Com io.probe.bits.payload.addr := xact.addr io.probe.bits.header.dst := UFix(0) io.grant.bits.payload.data := io.mem_resp.bits.data - io.grant.bits.payload.g_type := co.getGrantType(xact.a_type, init_sharer_cnt_) + io.grant.bits.payload.g_type := grant_type io.grant.bits.payload.client_xact_id := xact.client_xact_id io.grant.bits.payload.master_xact_id := UFix(id) - io.grant.bits.payload.require_ack := all_grants_require_acks io.grant.bits.header.dst := init_client_id_ io.grant.valid := (io.mem_resp.valid && (UFix(id) === io.mem_resp.bits.tag)) io.acquire.ready := Bool(false) @@ -821,12 +886,12 @@ class XactTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends Com doMemReqRead(io.mem_req_cmd, x_needs_read) } . otherwise { state := Mux(co.needsAckReply(xact.a_type, UFix(0)), s_ack, - Mux(all_grants_require_acks, s_busy, s_idle)) + Mux(co.requiresAck(io.grant.bits.payload), s_busy, s_idle)) } } is(s_ack) { io.grant.valid := Bool(true) - when(io.grant.ready) { state := Mux(all_grants_require_acks, s_busy, s_idle) } + when(io.grant.ready) { state := Mux(co.requiresAck(io.grant.bits.payload), s_busy, s_idle) } } is(s_busy) { // Nothing left to do but wait for transaction to complete when (io.free) { @@ -834,6 +899,12 @@ class XactTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends Com } } } +} + +trait MemoryRequestGenerator { + val mem_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES))) + val mem_cnt_next = mem_cnt + UFix(1) + val mem_cnt_max = ~UFix(0, width = log2Up(REFILL_CYCLES)) def doMemReqWrite[T <: Data](req_cmd: FIFOIO[MemReqCmd], req_data: FIFOIO[MemData], lock: Bool, data: FIFOIO[LogicalNetworkIO[T]], trigger: Bool, cmd_sent: Bool, pop_dep: Bool, at_front_of_dep_queue: Bool) { req_cmd.bits.rw := Bool(true) From 9f0ccbeac58c32ae2416e030d53dc656969fb7a1 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 28 Feb 2013 18:13:41 -0800 Subject: [PATCH 3/7] writebacks on release network pass asm tests and bmarks --- uncore/src/coherence.scala | 213 +++++++++++++++++-------------------- 1 file changed, 100 insertions(+), 113 deletions(-) diff --git a/uncore/src/coherence.scala b/uncore/src/coherence.scala index e1cc453e..effba2e9 100644 --- a/uncore/src/coherence.scala +++ b/uncore/src/coherence.scala @@ -28,20 +28,21 @@ abstract class CoherencePolicy { def getAcquireTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix def getAcquireTypeOnSecondaryMiss(cmd: Bits, state: UFix, outstanding: Acquire): UFix - def getAcquireTypeOnCacheControl(cmd: Bits): Bits - def getAcquireTypeOnWriteback(): Bits + def getReleaseTypeOnCacheControl(cmd: Bits): Bits + def getReleaseTypeOnVoluntaryWriteback(): Bits def getVoluntaryWriteback(addr: UFix, client_id: UFix, master_id: UFix): Release - def newRelease (incoming: Probe, state: UFix): Release + def newRelease (incoming: Probe, state: UFix, id: UFix): Release - def messageHasData (reply: Release): Bool + def messageHasData (rel: Release): Bool def messageHasData (acq: Acquire): Bool - def messageHasData (reply: Grant): Bool + def messageHasData (grant: Grant): Bool def messageUpdatesDataArray (reply: Grant): Bool def messageIsUncached(acq: Acquire): Bool def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool def isVoluntary(rel: Release): Bool + def isVoluntary(gnt: Grant): Bool def getGrantType(a_type: UFix, count: UFix): Bits def getGrantType(rel: Release, count: UFix): Bits def getProbeType(a_type: UFix, global_state: UFix): UFix @@ -50,6 +51,9 @@ abstract class CoherencePolicy { def needsAckReply(a_type: UFix, global_state: UFix): Bool def requiresAck(grant: Grant): Bool def requiresAck(release: Release): Bool + def pendingVoluntaryReleaseIsSufficient(r_type: UFix, p_type: UFix): Bool + + def uFixListContains(list: List[UFix], elem: UFix): Bool = list.map(elem === _).reduceLeft(_||_) } trait UncachedTransactions { @@ -66,13 +70,8 @@ abstract class CoherencePolicyWithUncached extends CoherencePolicy with Uncached abstract class IncoherentPolicy extends CoherencePolicy { // UNIMPLEMENTED def newStateOnProbe(incoming: Probe, state: UFix): Bits = state - def newRelease (incoming: Probe, state: UFix): Release = { - val reply = new Release - reply.r_type := UFix(0) - reply.master_xact_id := UFix(0) - reply - } - def messageHasData (reply: Release) = Bool(false) + def newRelease (incoming: Probe, state: UFix, id: UFix): Release = Release( UFix(0), UFix(0), UFix(0), UFix(0)) + def messageHasData (rel: Release) = Bool(false) def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool = Bool(false) def getGrantType(a_type: UFix, count: UFix): Bits = Bits(0) def getGrantType(rel: Release, count: UFix): Bits = Bits(0) @@ -82,15 +81,19 @@ abstract class IncoherentPolicy extends CoherencePolicy { def needsAckReply(a_type: UFix, global_state: UFix): Bool = Bool(false) def requiresAck(grant: Grant) = Bool(true) def requiresAck(release: Release) = Bool(false) + def pendingVoluntaryReleaseIsSufficient(r_type: UFix, p_type: UFix): Bool = Bool(false) + } class ThreeStateIncoherence extends IncoherentPolicy { val tileInvalid :: tileClean :: tileDirty :: Nil = Enum(3){ UFix() } val acquireReadClean :: acquireReadDirty :: acquireWriteback :: Nil = Enum(3){ UFix() } - val grantData :: grantAck :: Nil = Enum(2){ UFix() } + val grantVoluntaryAck :: grantData :: grantAck :: Nil = Enum(3){ UFix() } val releaseVoluntaryInvalidateData :: releaseInvalidateAck :: Nil = Enum(2){ UFix() } - val uncachedTypeList = List() - val hasDataTypeList = List(acquireWriteback) + val uncachedAcquireTypeList = List() + val hasDataAcquireTypeList = List(acquireWriteback) + val hasDataReleaseTypeList = List(acquireWriteback) + val hasDataGrantTypeList = List(grantData) def isHit ( cmd: Bits, state: UFix): Bool = (state === tileClean || state === tileDirty) def isValid (state: UFix): Bool = state != tileInvalid @@ -116,6 +119,7 @@ class ThreeStateIncoherence extends IncoherentPolicy { def getVoluntaryWriteback(addr: UFix, client_id: UFix, master_id: UFix) = Release(releaseVoluntaryInvalidateData, addr, client_id, master_id) def isVoluntary(rel: Release) = rel.r_type === releaseVoluntaryInvalidateData + def isVoluntary(gnt: Grant) = gnt.g_type === grantVoluntaryAck def getAcquireTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = { val (read, write) = cpuCmdToRW(cmd) @@ -125,13 +129,13 @@ class ThreeStateIncoherence extends IncoherentPolicy { val (read, write) = cpuCmdToRW(cmd) Mux(write, acquireReadDirty, outstanding.a_type) } - def getAcquireTypeOnCacheControl(cmd: Bits): Bits = acquireWriteback //TODO - def getAcquireTypeOnWriteback(): Bits = acquireWriteback + def getReleaseTypeOnCacheControl(cmd: Bits): Bits = releaseVoluntaryInvalidateData // TODO + def getReleaseTypeOnVoluntaryWriteback(): Bits = releaseVoluntaryInvalidateData - def messageHasData (init: Acquire): Bool = hasDataTypeList.map(t => init.a_type === t).reduceLeft(_||_) - def messageHasData (reply: Grant) = (reply.g_type === grantData) + def messageHasData (acq: Acquire): Bool = uFixListContains(hasDataAcquireTypeList, acq.a_type) + def messageHasData (grant: Grant): Bool = uFixListContains(hasDataGrantTypeList, grant.g_type) def messageUpdatesDataArray (reply: Grant) = (reply.g_type === grantData) - def messageIsUncached(init: Acquire): Bool = uncachedTypeList.map(t => init.a_type === t).reduceLeft(_||_) + def messageIsUncached(acq: Acquire): Bool = uFixListContains(uncachedAcquireTypeList, acq.a_type) } class MICoherence extends CoherencePolicyWithUncached { @@ -143,8 +147,10 @@ class MICoherence extends CoherencePolicyWithUncached { val grantVoluntaryAck :: grantReadExclusive :: grantReadUncached :: grantWriteUncached :: grantReadWordUncached :: grantWriteWordUncached :: grantAtomicUncached :: Nil = Enum(7){ UFix() } val probeInvalidate :: probeCopy :: Nil = Enum(2){ UFix() } val releaseVoluntaryInvalidateData :: releaseInvalidateData :: releaseCopyData :: releaseInvalidateAck :: releaseCopyAck :: Nil = Enum(5){ UFix() } - val uncachedTypeList = List(acquireReadUncached, acquireWriteUncached, grantReadWordUncached, acquireWriteWordUncached, acquireAtomicUncached) - val hasDataTypeList = List(acquireWriteUncached, acquireWriteWordUncached, acquireAtomicUncached) + val uncachedAcquireTypeList = List(acquireReadUncached, acquireWriteUncached, acquireReadWordUncached, acquireWriteWordUncached, acquireAtomicUncached) + val hasDataAcquireTypeList = List(acquireWriteUncached, acquireWriteWordUncached, acquireAtomicUncached) + val hasDataReleaseTypeList = List(releaseVoluntaryInvalidateData, releaseInvalidateData, releaseCopyData) + val hasDataGrantTypeList = List(grantReadExclusive, grantReadUncached, grantReadWordUncached, grantAtomicUncached) def isHit (cmd: Bits, state: UFix): Bool = state != tileInvalid def isValid (state: UFix): Bool = state != tileInvalid @@ -194,14 +200,14 @@ class MICoherence extends CoherencePolicyWithUncached { def getVoluntaryWriteback(addr: UFix, client_id: UFix, master_id: UFix) = Release(releaseVoluntaryInvalidateData, addr, client_id, master_id) def isUncachedReadTransaction(acq: Acquire) = acq.a_type === acquireReadUncached def isVoluntary(rel: Release) = rel.r_type === releaseVoluntaryInvalidateData + def isVoluntary(gnt: Grant) = gnt.g_type === grantVoluntaryAck def getAcquireTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = acquireReadExclusive def getAcquireTypeOnSecondaryMiss(cmd: Bits, state: UFix, outstanding: Acquire): UFix = acquireReadExclusive - def getAcquireTypeOnCacheControl(cmd: Bits): Bits = acquireWriteUncached - def getAcquireTypeOnWriteback(): Bits = getAcquireTypeOnCacheControl(M_INV) + def getReleaseTypeOnCacheControl(cmd: Bits): Bits = releaseVoluntaryInvalidateData // TODO + def getReleaseTypeOnVoluntaryWriteback(): Bits = getReleaseTypeOnCacheControl(M_INV) - def newRelease (incoming: Probe, state: UFix): Release = { - val reply = new Release + def newRelease (incoming: Probe, state: UFix, id: UFix): Release = { val with_data = MuxLookup(incoming.p_type, releaseInvalidateData, Array( probeInvalidate -> releaseInvalidateData, probeCopy -> releaseCopyData @@ -210,23 +216,16 @@ class MICoherence extends CoherencePolicyWithUncached { probeInvalidate -> releaseInvalidateAck, probeCopy -> releaseCopyAck )) - reply.r_type := Mux(needsWriteback(state), with_data, without_data) - reply.master_xact_id := incoming.master_xact_id - reply + Release( Mux(needsWriteback(state), with_data, without_data), incoming.addr, id, incoming.master_xact_id) } - def messageHasData (reply: Release): Bool = { - (reply.r_type === releaseInvalidateData || - reply.r_type === releaseCopyData) - } - def messageHasData (acq: Acquire): Bool = hasDataTypeList.map(t => acq.a_type === t).reduceLeft(_||_) - def messageHasData (reply: Grant): Bool = { - (reply.g_type != grantWriteUncached && reply.g_type != grantWriteWordUncached) - } + def messageHasData (rel: Release): Bool = uFixListContains(hasDataReleaseTypeList, rel.r_type) + def messageHasData (acq: Acquire): Bool = uFixListContains(hasDataAcquireTypeList, acq.a_type) + def messageHasData (grant: Grant): Bool = uFixListContains(hasDataGrantTypeList, grant.g_type) def messageUpdatesDataArray (reply: Grant): Bool = { (reply.g_type === grantReadExclusive) } - def messageIsUncached(acq: Acquire): Bool = uncachedTypeList.map(t => acq.a_type === t).reduceLeft(_||_) + def messageIsUncached(acq: Acquire): Bool = uFixListContains(uncachedAcquireTypeList, acq.a_type) def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool = (addr1 === addr2) @@ -269,6 +268,7 @@ class MICoherence extends CoherencePolicyWithUncached { } def requiresAck(grant: Grant) = Bool(true) def requiresAck(release: Release) = Bool(false) + def pendingVoluntaryReleaseIsSufficient(r_type: UFix, p_type: UFix): Bool = (r_type === releaseVoluntaryInvalidateData) } class MEICoherence extends CoherencePolicyWithUncached { @@ -280,8 +280,11 @@ class MEICoherence extends CoherencePolicyWithUncached { val grantVoluntaryAck :: grantReadExclusive :: grantReadUncached :: grantWriteUncached :: grantReadExclusiveAck :: grantReadWordUncached :: grantWriteWordUncached :: grantAtomicUncached :: Nil = Enum(8){ UFix() } val probeInvalidate :: probeDowngrade :: probeCopy :: Nil = Enum(3){ UFix() } val releaseVoluntaryInvalidateData :: releaseInvalidateData :: releaseDowngradeData :: releaseCopyData :: releaseInvalidateAck :: releaseDowngradeAck :: releaseCopyAck :: Nil = Enum(7){ UFix() } - val uncachedTypeList = List(acquireReadUncached, acquireWriteUncached, grantReadWordUncached, acquireWriteWordUncached, acquireAtomicUncached) - val hasDataTypeList = List(acquireWriteUncached, acquireWriteWordUncached, acquireAtomicUncached) + + val uncachedAcquireTypeList = List(acquireReadUncached, acquireWriteUncached, acquireReadWordUncached, acquireWriteWordUncached, acquireAtomicUncached) + val hasDataAcquireTypeList = List(acquireWriteUncached, acquireWriteWordUncached, acquireAtomicUncached) + val hasDataReleaseTypeList = List(releaseVoluntaryInvalidateData, releaseInvalidateData, releaseDowngradeData, releaseCopyData) + val hasDataGrantTypeList = List(grantReadExclusive, grantReadUncached, grantReadWordUncached, grantAtomicUncached) def isHit (cmd: Bits, state: UFix): Bool = state != tileInvalid def isValid (state: UFix): Bool = state != tileInvalid @@ -340,6 +343,7 @@ class MEICoherence extends CoherencePolicyWithUncached { def getVoluntaryWriteback(addr: UFix, client_id: UFix, master_id: UFix) = Release(releaseVoluntaryInvalidateData, addr, client_id, master_id) def isUncachedReadTransaction(acq: Acquire) = acq.a_type === acquireReadUncached def isVoluntary(rel: Release) = rel.r_type === releaseVoluntaryInvalidateData + def isVoluntary(gnt: Grant) = gnt.g_type === grantVoluntaryAck def getAcquireTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = { val (read, write) = cpuCmdToRW(cmd) @@ -349,11 +353,10 @@ class MEICoherence extends CoherencePolicyWithUncached { val (read, write) = cpuCmdToRW(cmd) Mux(write, acquireReadExclusiveDirty, outstanding.a_type) } - def getAcquireTypeOnCacheControl(cmd: Bits): Bits = acquireWriteUncached - def getAcquireTypeOnWriteback(): Bits = getAcquireTypeOnCacheControl(M_INV) + def getReleaseTypeOnCacheControl(cmd: Bits): Bits = releaseVoluntaryInvalidateData // TODO + def getReleaseTypeOnVoluntaryWriteback(): Bits = getReleaseTypeOnCacheControl(M_INV) - def newRelease (incoming: Probe, state: UFix): Release = { - val reply = new Release + def newRelease (incoming: Probe, state: UFix, id: UFix): Release = { val with_data = MuxLookup(incoming.p_type, releaseInvalidateData, Array( probeInvalidate -> releaseInvalidateData, probeDowngrade -> releaseDowngradeData, @@ -364,24 +367,16 @@ class MEICoherence extends CoherencePolicyWithUncached { probeDowngrade -> releaseDowngradeAck, probeCopy -> releaseCopyAck )) - reply.r_type := Mux(needsWriteback(state), with_data, without_data) - reply.master_xact_id := incoming.master_xact_id - reply + Release( Mux(needsWriteback(state), with_data, without_data), incoming.addr, id, incoming.master_xact_id) } - def messageHasData (reply: Release): Bool = { - (reply.r_type === releaseInvalidateData || - reply.r_type === releaseDowngradeData || - reply.r_type === releaseCopyData) - } - def messageHasData (acq: Acquire): Bool = hasDataTypeList.map(t => acq.a_type === t).reduceLeft(_||_) - def messageHasData (reply: Grant): Bool = { - (reply.g_type != grantWriteUncached && reply.g_type != grantReadExclusiveAck && reply.g_type != grantWriteWordUncached) - } + def messageHasData (rel: Release): Bool = uFixListContains(hasDataReleaseTypeList, rel.r_type) + def messageHasData (acq: Acquire): Bool = uFixListContains(hasDataAcquireTypeList, acq.a_type) + def messageHasData (grant: Grant): Bool = uFixListContains(hasDataGrantTypeList, grant.g_type) def messageUpdatesDataArray (reply: Grant): Bool = { (reply.g_type === grantReadExclusive) } - def messageIsUncached(init: Acquire): Bool = uncachedTypeList.map(t => init.a_type === t).reduceLeft(_||_) + def messageIsUncached(acq: Acquire): Bool = uFixListContains(uncachedAcquireTypeList, acq.a_type) def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool = (addr1 === addr2) @@ -426,6 +421,8 @@ class MEICoherence extends CoherencePolicyWithUncached { } def requiresAck(grant: Grant) = Bool(true) def requiresAck(release: Release) = Bool(false) + + def pendingVoluntaryReleaseIsSufficient(r_type: UFix, p_type: UFix): Bool = (r_type === releaseVoluntaryInvalidateData) } class MSICoherence extends CoherencePolicyWithUncached { @@ -437,8 +434,10 @@ class MSICoherence extends CoherencePolicyWithUncached { val grantVoluntaryAck :: grantReadShared :: grantReadExclusive :: grantReadUncached :: grantWriteUncached :: grantReadExclusiveAck :: grantReadWordUncached :: grantWriteWordUncached :: grantAtomicUncached :: Nil = Enum(9){ UFix() } val probeInvalidate :: probeDowngrade :: probeCopy :: Nil = Enum(3){ UFix() } val releaseVoluntaryInvalidateData :: releaseInvalidateData :: releaseDowngradeData :: releaseCopyData :: releaseInvalidateAck :: releaseDowngradeAck :: releaseCopyAck :: Nil = Enum(7){ UFix() } - val uncachedTypeList = List(acquireReadUncached, acquireWriteUncached, grantReadWordUncached, acquireWriteWordUncached, acquireAtomicUncached) - val hasDataTypeList = List(acquireWriteUncached, acquireWriteWordUncached, acquireAtomicUncached) + val uncachedAcquireTypeList = List(acquireReadUncached, acquireWriteUncached, acquireReadWordUncached, acquireWriteWordUncached, acquireAtomicUncached) + val hasDataAcquireTypeList = List(acquireWriteUncached, acquireWriteWordUncached, acquireAtomicUncached) + val hasDataReleaseTypeList = List(releaseVoluntaryInvalidateData, releaseInvalidateData, releaseDowngradeData, releaseCopyData) + val hasDataGrantTypeList = List(grantReadShared, grantReadExclusive, grantReadUncached, grantReadWordUncached, grantAtomicUncached) def isHit (cmd: Bits, state: UFix): Bool = { val (read, write) = cpuCmdToRW(cmd) @@ -504,6 +503,7 @@ class MSICoherence extends CoherencePolicyWithUncached { def getVoluntaryWriteback(addr: UFix, client_id: UFix, master_id: UFix) = Release(releaseVoluntaryInvalidateData, addr, client_id, master_id) def isUncachedReadTransaction(acq: Acquire) = acq.a_type === acquireReadUncached def isVoluntary(rel: Release) = rel.r_type === releaseVoluntaryInvalidateData + def isVoluntary(gnt: Grant) = gnt.g_type === grantVoluntaryAck def getAcquireTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = { val (read, write) = cpuCmdToRW(cmd) @@ -513,11 +513,10 @@ class MSICoherence extends CoherencePolicyWithUncached { val (read, write) = cpuCmdToRW(cmd) Mux(write, acquireReadExclusive, outstanding.a_type) } - def getAcquireTypeOnCacheControl(cmd: Bits): Bits = acquireWriteUncached - def getAcquireTypeOnWriteback(): Bits = getAcquireTypeOnCacheControl(M_INV) + def getReleaseTypeOnCacheControl(cmd: Bits): Bits = releaseVoluntaryInvalidateData // TODO + def getReleaseTypeOnVoluntaryWriteback(): Bits = getReleaseTypeOnCacheControl(M_INV) - def newRelease (incoming: Probe, state: UFix): Release = { - val reply = new Release + def newRelease (incoming: Probe, state: UFix, id: UFix): Release = { val with_data = MuxLookup(incoming.p_type, releaseInvalidateData, Array( probeInvalidate -> releaseInvalidateData, probeDowngrade -> releaseDowngradeData, @@ -528,24 +527,16 @@ class MSICoherence extends CoherencePolicyWithUncached { probeDowngrade -> releaseDowngradeAck, probeCopy -> releaseCopyAck )) - reply.r_type := Mux(needsWriteback(state), with_data, without_data) - reply.master_xact_id := incoming.master_xact_id - reply + Release( Mux(needsWriteback(state), with_data, without_data), incoming.addr, id, incoming.master_xact_id) } - def messageHasData (reply: Release): Bool = { - (reply.r_type === releaseInvalidateData || - reply.r_type === releaseDowngradeData || - reply.r_type === releaseCopyData) - } - def messageHasData (acq: Acquire): Bool = hasDataTypeList.map(t => acq.a_type === t).reduceLeft(_||_) - def messageHasData (reply: Grant): Bool = { - (reply.g_type != grantWriteUncached && reply.g_type != grantReadExclusiveAck && reply.g_type != grantWriteWordUncached) - } + def messageHasData (rel: Release): Bool = uFixListContains(hasDataReleaseTypeList, rel.r_type) + def messageHasData (acq: Acquire): Bool = uFixListContains(hasDataAcquireTypeList, acq.a_type) + def messageHasData (grant: Grant): Bool = uFixListContains(hasDataGrantTypeList, grant.g_type) def messageUpdatesDataArray (reply: Grant): Bool = { (reply.g_type === grantReadShared || reply.g_type === grantReadExclusive) } - def messageIsUncached(acq: Acquire): Bool = uncachedTypeList.map(t => acq.a_type === t).reduceLeft(_||_) + def messageIsUncached(acq: Acquire): Bool = uFixListContains(uncachedAcquireTypeList, acq.a_type) def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool = (addr1 === addr2) @@ -587,6 +578,8 @@ class MSICoherence extends CoherencePolicyWithUncached { } def requiresAck(grant: Grant) = Bool(true) def requiresAck(release: Release) = Bool(false) + + def pendingVoluntaryReleaseIsSufficient(r_type: UFix, p_type: UFix): Bool = (r_type === releaseVoluntaryInvalidateData) } class MESICoherence extends CoherencePolicyWithUncached { @@ -598,8 +591,11 @@ class MESICoherence extends CoherencePolicyWithUncached { val grantVoluntaryAck :: grantReadShared :: grantReadExclusive :: grantReadUncached :: grantWriteUncached :: grantReadExclusiveAck :: grantReadWordUncached :: grantWriteWordUncached :: grantAtomicUncached :: Nil = Enum(9){ UFix() } val probeInvalidate :: probeDowngrade :: probeCopy :: Nil = Enum(3){ UFix() } val releaseVoluntaryInvalidateData :: releaseInvalidateData :: releaseDowngradeData :: releaseCopyData :: releaseInvalidateAck :: releaseDowngradeAck :: releaseCopyAck :: Nil = Enum(7){ UFix() } - val uncachedTypeList = List(acquireReadUncached, acquireWriteUncached, acquireReadWordUncached, acquireWriteWordUncached, acquireAtomicUncached) - val hasDataTypeList = List(acquireWriteUncached, acquireWriteWordUncached, acquireAtomicUncached) + + val uncachedAcquireTypeList = List(acquireReadUncached, acquireWriteUncached, acquireReadWordUncached, acquireWriteWordUncached, acquireAtomicUncached) + val hasDataAcquireTypeList = List(acquireWriteUncached, acquireWriteWordUncached, acquireAtomicUncached) + val hasDataReleaseTypeList = List(releaseVoluntaryInvalidateData, releaseInvalidateData, releaseDowngradeData, releaseCopyData) + val hasDataGrantTypeList = List(grantReadShared, grantReadExclusive, grantReadUncached, grantReadWordUncached, grantAtomicUncached) def isHit (cmd: Bits, state: UFix): Bool = { val (read, write) = cpuCmdToRW(cmd) @@ -665,6 +661,7 @@ class MESICoherence extends CoherencePolicyWithUncached { def getVoluntaryWriteback(addr: UFix, client_id: UFix, master_id: UFix) = Release(releaseVoluntaryInvalidateData, addr, client_id, master_id) def isUncachedReadTransaction(acq: Acquire) = acq.a_type === acquireReadUncached def isVoluntary(rel: Release) = rel.r_type === releaseVoluntaryInvalidateData + def isVoluntary(gnt: Grant) = gnt.g_type === grantVoluntaryAck def getAcquireTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = { val (read, write) = cpuCmdToRW(cmd) @@ -674,11 +671,10 @@ class MESICoherence extends CoherencePolicyWithUncached { val (read, write) = cpuCmdToRW(cmd) Mux(write, acquireReadExclusive, outstanding.a_type) } - def getAcquireTypeOnCacheControl(cmd: Bits): Bits = acquireWriteUncached - def getAcquireTypeOnWriteback(): Bits = getAcquireTypeOnCacheControl(M_INV) + def getReleaseTypeOnCacheControl(cmd: Bits): Bits = releaseVoluntaryInvalidateData // TODO + def getReleaseTypeOnVoluntaryWriteback(): Bits = getReleaseTypeOnCacheControl(M_INV) - def newRelease (incoming: Probe, state: UFix): Release = { - val reply = new Release + def newRelease (incoming: Probe, state: UFix, id: UFix): Release = { val with_data = MuxLookup(incoming.p_type, releaseInvalidateData, Array( probeInvalidate -> releaseInvalidateData, probeDowngrade -> releaseDowngradeData, @@ -689,24 +685,16 @@ class MESICoherence extends CoherencePolicyWithUncached { probeDowngrade -> releaseDowngradeAck, probeCopy -> releaseCopyAck )) - reply.r_type := Mux(needsWriteback(state), with_data, without_data) - reply.master_xact_id := incoming.master_xact_id - reply + Release( Mux(needsWriteback(state), with_data, without_data), incoming.addr, id, incoming.master_xact_id) } - def messageHasData (reply: Release): Bool = { - (reply.r_type === releaseInvalidateData || - reply.r_type === releaseDowngradeData || - reply.r_type === releaseCopyData) - } - def messageHasData (acq: Acquire): Bool = hasDataTypeList.map(t => acq.a_type === t).reduceLeft(_||_) - def messageHasData (reply: Grant): Bool = { - (reply.g_type != grantWriteUncached && reply.g_type != grantReadExclusiveAck && reply.g_type != grantWriteWordUncached) - } + def messageHasData (rel: Release): Bool = uFixListContains(hasDataReleaseTypeList, rel.r_type) + def messageHasData (acq: Acquire): Bool = uFixListContains(hasDataAcquireTypeList, acq.a_type) + def messageHasData (grant: Grant): Bool = uFixListContains(hasDataGrantTypeList, grant.g_type) def messageUpdatesDataArray (reply: Grant): Bool = { (reply.g_type === grantReadShared || reply.g_type === grantReadExclusive) } - def messageIsUncached(acq: Acquire): Bool = uncachedTypeList.map(t => acq.a_type === t).reduceLeft(_||_) + def messageIsUncached(acq: Acquire): Bool = uFixListContains(uncachedAcquireTypeList, acq.a_type) def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool = (addr1 === addr2) @@ -752,6 +740,8 @@ class MESICoherence extends CoherencePolicyWithUncached { def requiresAck(grant: Grant) = Bool(true) def requiresAck(release: Release) = Bool(false) + + def pendingVoluntaryReleaseIsSufficient(r_type: UFix, p_type: UFix): Bool = (r_type === releaseVoluntaryInvalidateData) } class MigratoryCoherence extends CoherencePolicyWithUncached { @@ -762,10 +752,11 @@ class MigratoryCoherence extends CoherencePolicyWithUncached { val grantVoluntaryAck :: grantReadShared :: grantReadExclusive :: grantReadUncached :: grantWriteUncached :: grantReadExclusiveAck :: grantReadWordUncached :: grantWriteWordUncached :: grantAtomicUncached :: grantReadMigratory :: Nil = Enum(10){ UFix() } val probeInvalidate :: probeDowngrade :: probeCopy :: probeInvalidateOthers :: Nil = Enum(4){ UFix() } val releaseVoluntaryInvalidateData :: releaseInvalidateData :: releaseDowngradeData :: releaseCopyData :: releaseInvalidateAck :: releaseDowngradeAck :: releaseCopyAck :: releaseDowngradeDataMigratory :: releaseDowngradeAckHasCopy :: releaseInvalidateDataMigratory :: releaseInvalidateAckMigratory :: Nil = Enum(11){ UFix() } - val uncachedTypeList = List(acquireReadUncached, acquireWriteUncached, acquireReadWordUncached, acquireWriteWordUncached, acquireAtomicUncached) - val hasDataTypeList = List(acquireWriteUncached, acquireWriteWordUncached, acquireAtomicUncached) - def uFixListContains(list: List[UFix], elem: UFix): Bool = list.map(elem === _).reduceLeft(_||_) + val uncachedAcquireTypeList = List(acquireReadUncached, acquireWriteUncached, acquireReadWordUncached, acquireWriteWordUncached, acquireAtomicUncached) + val hasDataAcquireTypeList = List(acquireWriteUncached, acquireWriteWordUncached, acquireAtomicUncached) + val hasDataGrantTypeList = List(grantReadShared, grantReadExclusive, grantReadUncached, grantReadMigratory, grantReadWordUncached, grantAtomicUncached) + val hasDataReleaseTypeList = List(releaseVoluntaryInvalidateData, releaseInvalidateData, releaseDowngradeData, releaseCopyData, releaseInvalidateDataMigratory, releaseDowngradeDataMigratory) def isHit (cmd: Bits, state: UFix): Bool = { val (read, write) = cpuCmdToRW(cmd) @@ -844,6 +835,7 @@ class MigratoryCoherence extends CoherencePolicyWithUncached { def getVoluntaryWriteback(addr: UFix, client_id: UFix, master_id: UFix) = Release(releaseVoluntaryInvalidateData, addr, client_id, master_id) def isUncachedReadTransaction(acq: Acquire) = acq.a_type === acquireReadUncached def isVoluntary(rel: Release) = rel.r_type === releaseVoluntaryInvalidateData + def isVoluntary(gnt: Grant) = gnt.g_type === grantVoluntaryAck def getAcquireTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = { val (read, write) = cpuCmdToRW(cmd) @@ -853,12 +845,11 @@ class MigratoryCoherence extends CoherencePolicyWithUncached { val (read, write) = cpuCmdToRW(cmd) Mux(write, Mux(state === tileInvalid, acquireReadExclusive, acquireInvalidateOthers), outstanding.a_type) } - def getAcquireTypeOnCacheControl(cmd: Bits): Bits = acquireWriteUncached - def getAcquireTypeOnWriteback(): Bits = getAcquireTypeOnCacheControl(M_INV) + def getReleaseTypeOnCacheControl(cmd: Bits): Bits = releaseVoluntaryInvalidateData // TODO + def getReleaseTypeOnVoluntaryWriteback(): Bits = getReleaseTypeOnCacheControl(M_INV) - def newRelease (incoming: Probe, state: UFix): Release = { + def newRelease (incoming: Probe, state: UFix, id: UFix): Release = { Assert( incoming.p_type === probeInvalidateOthers && needsWriteback(state), "Bad probe request type, should be impossible.") - val reply = new Release() val with_data = MuxLookup(incoming.p_type, releaseInvalidateData, Array( probeInvalidate -> Mux(uFixListContains(List(tileExclusiveDirty, tileMigratoryDirty), state), releaseInvalidateDataMigratory, releaseInvalidateData), @@ -871,22 +862,16 @@ class MigratoryCoherence extends CoherencePolicyWithUncached { probeDowngrade -> Mux(state != tileInvalid, releaseDowngradeAckHasCopy, releaseDowngradeAck), probeCopy -> releaseCopyAck )) - reply.r_type := Mux(needsWriteback(state), with_data, without_data) - reply.master_xact_id := incoming.master_xact_id - reply + Release( Mux(needsWriteback(state), with_data, without_data), incoming.addr, id, incoming.master_xact_id) } - def messageHasData (reply: Release): Bool = { - uFixListContains(List(releaseInvalidateData, releaseDowngradeData, releaseCopyData, releaseInvalidateDataMigratory, releaseDowngradeDataMigratory), reply.r_type) - } - def messageHasData (acq: Acquire): Bool = uFixListContains(hasDataTypeList, acq.a_type) - def messageHasData (reply: Grant): Bool = { - uFixListContains(List(grantReadShared, grantReadExclusive, grantReadUncached, grantReadMigratory, grantReadWordUncached, grantAtomicUncached), reply.g_type) - } + def messageHasData (acq: Acquire): Bool = uFixListContains(hasDataAcquireTypeList, acq.a_type) + def messageHasData (rel: Release): Bool = uFixListContains(hasDataReleaseTypeList, rel.r_type) + def messageHasData (grant: Grant): Bool = uFixListContains(hasDataGrantTypeList, grant.g_type) def messageUpdatesDataArray (reply: Grant): Bool = { uFixListContains(List(grantReadShared, grantReadExclusive, grantReadMigratory), reply.g_type) } - def messageIsUncached(acq: Acquire): Bool = uFixListContains(uncachedTypeList, acq.a_type) + def messageIsUncached(acq: Acquire): Bool = uFixListContains(uncachedAcquireTypeList, acq.a_type) def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool = (addr1 === addr2) @@ -933,4 +918,6 @@ class MigratoryCoherence extends CoherencePolicyWithUncached { } def requiresAck(grant: Grant) = Bool(true) def requiresAck(release: Release) = Bool(false) + + def pendingVoluntaryReleaseIsSufficient(r_type: UFix, p_type: UFix): Bool = (r_type === releaseVoluntaryInvalidateData) } From 7b019cb0da4f2699e9b1fc45b8f21fc7adf9c96d Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 19 Mar 2013 15:30:23 -0700 Subject: [PATCH 4/7] rmeove aborts --- uncore/src/tilelink.scala | 5 -- uncore/src/uncore.scala | 96 ++++----------------------------------- 2 files changed, 8 insertions(+), 93 deletions(-) diff --git a/uncore/src/tilelink.scala b/uncore/src/tilelink.scala index 51b64b16..73bf8aff 100644 --- a/uncore/src/tilelink.scala +++ b/uncore/src/tilelink.scala @@ -70,10 +70,6 @@ object Acquire class AcquireData extends MemData -class Abort extends Bundle { - val client_xact_id = Bits(width = CLIENT_XACT_ID_BITS) -} - class Probe extends PhysicalAddress { val p_type = Bits(width = PROBE_TYPE_MAX_BITS) val master_xact_id = Bits(width = MASTER_XACT_ID_BITS) @@ -115,7 +111,6 @@ class MasterSourcedIO[T <: Data]()(data: => T) extends DirectionalFIFOIO()(data) class TileLinkIO(implicit conf: LogicalNetworkConfiguration) extends Bundle { val acquire = (new ClientSourcedIO){(new LogicalNetworkIO){new Acquire }} val acquire_data = (new ClientSourcedIO){(new LogicalNetworkIO){new AcquireData }} - val abort = (new MasterSourcedIO){(new LogicalNetworkIO){new Abort }} val probe = (new MasterSourcedIO){(new LogicalNetworkIO){new Probe }} val release = (new ClientSourcedIO){(new LogicalNetworkIO){new Release }} val release_data = (new ClientSourcedIO){(new LogicalNetworkIO){new ReleaseData }} diff --git a/uncore/src/uncore.scala b/uncore/src/uncore.scala index a439c7b6..8d1d396d 100644 --- a/uncore/src/uncore.scala +++ b/uncore/src/uncore.scala @@ -290,7 +290,6 @@ class CoherenceHubNull(implicit conf: CoherenceHubConfiguration) extends Coheren grant.bits.payload.data := io.mem.resp.bits.data grant.valid := io.mem.resp.valid || acquire.valid && is_write && io.mem.req_cmd.ready - io.tiles(0).abort.valid := Bool(false) io.tiles(0).grant_ack.ready := Bool(true) io.tiles(0).probe.valid := Bool(false) io.tiles(0).release.ready := Bool(true) @@ -427,51 +426,6 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co release_cnt_dec_arr(i)(j) := release.valid && (release.bits.payload.master_xact_id === UFix(i)) } } - - // Nack conflicting transaction init attempts - val s_idle :: s_abort_drain :: s_abort_send :: Nil = Enum(3){ UFix() } - val abort_state_arr = Vec(conf.ln.nTiles) { Reg(resetVal = s_idle) } - val want_to_abort_arr = Vec(conf.ln.nTiles) { Bool() } - for( j <- 0 until conf.ln.nTiles ) { - val acquire = io.tiles(j).acquire - val acquire_data = io.tiles(j).acquire_data - val x_abort = io.tiles(j).abort - val abort_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES))) - val conflicts = Vec(NGLOBAL_XACTS) { Bool() } - for( i <- 0 until NGLOBAL_XACTS) { - val t = trackerList(i).io - conflicts(i) := t.busy && acquire.valid && co.isCoherenceConflict(t.addr, acquire.bits.payload.addr) - } - x_abort.bits.payload.client_xact_id := acquire.bits.payload.client_xact_id - want_to_abort_arr(j) := acquire.valid && (conflicts.toBits.orR || busy_arr.toBits.andR || (!acquire_data_dep_list(j).io.enq.ready && co.messageHasData(acquire.bits.payload))) - - x_abort.valid := Bool(false) - switch(abort_state_arr(j)) { - is(s_idle) { - when(want_to_abort_arr(j)) { - when(co.messageHasData(acquire.bits.payload)) { - abort_state_arr(j) := s_abort_drain - } . otherwise { - abort_state_arr(j) := s_abort_send - } - } - } - is(s_abort_drain) { // raises acquire_data.ready below - when(acquire_data.valid) { - abort_cnt := abort_cnt + UFix(1) - when(abort_cnt === ~UFix(0, width = log2Up(REFILL_CYCLES))) { - abort_state_arr(j) := s_abort_send - } - } - } - is(s_abort_send) { // nothing is dequeued for now - x_abort.valid := Bool(true) - when(x_abort.ready) { // raises acquire.ready below - abort_state_arr(j) := s_idle - } - } - } - } // Handle transaction initiation requests // Only one allocation per cycle @@ -493,16 +447,14 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co val acquire = io.tiles(j).acquire val acquire_data = io.tiles(j).acquire_data val acquire_data_dep = acquire_data_dep_list(j).io.deq - val x_abort = io.tiles(j).abort - init_arb.io.in(j).valid := (abort_state_arr(j) === s_idle) && !want_to_abort_arr(j) && acquire.valid + init_arb.io.in(j).valid := acquire.valid init_arb.io.in(j).bits.acquire := acquire.bits.payload init_arb.io.in(j).bits.client_id := UFix(j) val pop_acquires = trackerList.map(_.io.pop_acquire(j).toBool) - val do_pop = foldR(pop_acquires)(_||_) - acquire_data_dep_list(j).io.enq.valid := do_pop && co.messageHasData(acquire.bits.payload) && (abort_state_arr(j) === s_idle) + acquire.ready := foldR(pop_acquires)(_||_) + acquire_data_dep_list(j).io.enq.valid := acquire.ready && co.messageHasData(acquire.bits.payload) acquire_data_dep_list(j).io.enq.bits.master_xact_id := OHToUFix(pop_acquires) - acquire.ready := (x_abort.valid && x_abort.ready) || do_pop - acquire_data.ready := (abort_state_arr(j) === s_abort_drain) || foldR(trackerList.map(_.io.pop_acquire_data(j).toBool))(_||_) + acquire_data.ready := foldR(trackerList.map(_.io.pop_acquire_data(j).toBool))(_||_) acquire_data_dep.ready := foldR(trackerList.map(_.io.pop_acquire_dep(j).toBool))(_||_) } @@ -552,61 +504,29 @@ class L2CoherenceAgent(implicit conf: CoherenceHubConfiguration) extends Coheren // Init requests may or may not have data val acquire = io.network.acquire val acquire_data = io.network.acquire_data - val x_abort = io.network.abort val x_dep_deq = acquire_data_dep_q.io.deq - val s_idle :: s_abort_drain :: s_abort_send :: Nil = Enum(3){ UFix() } - val abort_state = Reg(resetVal = s_idle) - val abort_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES))) val any_acquire_conflict = trackerList.map(_.io.has_acquire_conflict).reduce(_||_) val all_busy = trackerList.map(_.io.busy).reduce(_&&_) - val want_to_abort = acquire.valid && (any_acquire_conflict || all_busy || (!acquire_data_dep_q.io.enq.ready && co.messageHasData(acquire.bits.payload))) val alloc_arb = (new Arbiter(NGLOBAL_XACTS+1)) { Bool() } for( i <- 0 to NGLOBAL_XACTS ) { alloc_arb.io.in(i).valid := !trackerList(i).io.busy trackerList(i).io.acquire.bits := acquire.bits - trackerList(i).io.acquire.valid := (abort_state === s_idle) && !want_to_abort && acquire.valid && alloc_arb.io.in(i).ready + trackerList(i).io.acquire.valid := acquire.valid && alloc_arb.io.in(i).ready trackerList(i).io.acquire_data.bits := acquire_data.bits trackerList(i).io.acquire_data.valid := acquire_data.valid trackerList(i).io.acquire_data_dep.bits := x_dep_deq.bits trackerList(i).io.acquire_data_dep.valid := x_dep_deq.valid } - val pop_acquire = trackerList.map(_.io.acquire.ready).reduce(_||_) - acquire.ready := (x_abort.valid && x_abort.ready) || pop_acquire - acquire_data.ready := (abort_state === s_abort_drain) || trackerList.map(_.io.acquire_data.ready).reduce(_||_) - acquire_data_dep_q.io.enq.valid := pop_acquire && co.messageHasData(acquire.bits.payload) && (abort_state === s_idle) + acquire.ready := trackerList.map(_.io.acquire.ready).reduce(_||_) + acquire_data.ready := trackerList.map(_.io.acquire_data.ready).reduce(_||_) + acquire_data_dep_q.io.enq.valid := acquire.ready && co.messageHasData(acquire.bits.payload) acquire_data_dep_q.io.enq.bits.master_xact_id := OHToUFix(trackerList.map(_.io.acquire.ready)) x_dep_deq.ready := trackerList.map(_.io.acquire_data_dep.ready).reduce(_||_) alloc_arb.io.out.ready := acquire.valid - // Nack conflicting transaction init attempts - x_abort.bits.header.dst := acquire.bits.header.src - x_abort.bits.payload.client_xact_id := acquire.bits.payload.client_xact_id - x_abort.valid := Bool(false) - switch(abort_state) { - is(s_idle) { - when(want_to_abort) { - abort_state := Mux( co.messageHasData(acquire.bits.payload), s_abort_drain, s_abort_send) - } - } - is(s_abort_drain) { // raises acquire_data.ready below - when(acquire_data.valid) { - abort_cnt := abort_cnt + UFix(1) - when(abort_cnt === ~UFix(0, width = log2Up(REFILL_CYCLES))) { - abort_state := s_abort_send - } - } - } - is(s_abort_send) { // nothing is dequeued for now - x_abort.valid := Bool(true) - when(x_abort.ready) { // raises acquire.ready - abort_state := s_idle - } - } - } - // Handle probe request generation val probe_arb = (new Arbiter(NGLOBAL_XACTS+1)){(new LogicalNetworkIO){ new Probe }} for( i <- 0 to NGLOBAL_XACTS ) { From a7ae7e5758eea704ed284667df0295e9b304a30c Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 28 Feb 2013 19:49:05 -0800 Subject: [PATCH 5/7] Cleaned up self-probes --- uncore/src/coherence.scala | 7 +++++++ uncore/src/uncore.scala | 11 +++-------- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/uncore/src/coherence.scala b/uncore/src/coherence.scala index effba2e9..f7a75afc 100644 --- a/uncore/src/coherence.scala +++ b/uncore/src/coherence.scala @@ -49,6 +49,7 @@ abstract class CoherencePolicy { def needsMemRead(a_type: UFix, global_state: UFix): Bool def needsMemWrite(a_type: UFix, global_state: UFix): Bool def needsAckReply(a_type: UFix, global_state: UFix): Bool + def needsSelfProbe(acq: Acquire): Bool def requiresAck(grant: Grant): Bool def requiresAck(release: Release): Bool def pendingVoluntaryReleaseIsSufficient(r_type: UFix, p_type: UFix): Bool @@ -79,6 +80,7 @@ abstract class IncoherentPolicy extends CoherencePolicy { def needsMemRead(a_type: UFix, global_state: UFix): Bool = Bool(false) def needsMemWrite(a_type: UFix, global_state: UFix): Bool = Bool(false) def needsAckReply(a_type: UFix, global_state: UFix): Bool = Bool(false) + def needsSelfProbe(acq: Acquire) = Bool(false) def requiresAck(grant: Grant) = Bool(true) def requiresAck(release: Release) = Bool(false) def pendingVoluntaryReleaseIsSufficient(r_type: UFix, p_type: UFix): Bool = Bool(false) @@ -268,6 +270,7 @@ class MICoherence extends CoherencePolicyWithUncached { } def requiresAck(grant: Grant) = Bool(true) def requiresAck(release: Release) = Bool(false) + def needsSelfProbe(acq: Acquire) = acq.a_type === acquireReadUncached def pendingVoluntaryReleaseIsSufficient(r_type: UFix, p_type: UFix): Bool = (r_type === releaseVoluntaryInvalidateData) } @@ -421,6 +424,7 @@ class MEICoherence extends CoherencePolicyWithUncached { } def requiresAck(grant: Grant) = Bool(true) def requiresAck(release: Release) = Bool(false) + def needsSelfProbe(acq: Acquire) = acq.a_type === acquireReadUncached def pendingVoluntaryReleaseIsSufficient(r_type: UFix, p_type: UFix): Bool = (r_type === releaseVoluntaryInvalidateData) } @@ -578,6 +582,7 @@ class MSICoherence extends CoherencePolicyWithUncached { } def requiresAck(grant: Grant) = Bool(true) def requiresAck(release: Release) = Bool(false) + def needsSelfProbe(acq: Acquire) = acq.a_type === acquireReadUncached def pendingVoluntaryReleaseIsSufficient(r_type: UFix, p_type: UFix): Bool = (r_type === releaseVoluntaryInvalidateData) } @@ -740,6 +745,7 @@ class MESICoherence extends CoherencePolicyWithUncached { def requiresAck(grant: Grant) = Bool(true) def requiresAck(release: Release) = Bool(false) + def needsSelfProbe(acq: Acquire) = acq.a_type === acquireReadUncached def pendingVoluntaryReleaseIsSufficient(r_type: UFix, p_type: UFix): Bool = (r_type === releaseVoluntaryInvalidateData) } @@ -918,6 +924,7 @@ class MigratoryCoherence extends CoherencePolicyWithUncached { } def requiresAck(grant: Grant) = Bool(true) def requiresAck(release: Release) = Bool(false) + def needsSelfProbe(acq: Acquire) = acq.a_type === acquireReadUncached def pendingVoluntaryReleaseIsSufficient(r_type: UFix, p_type: UFix): Bool = (r_type === releaseVoluntaryInvalidateData) } diff --git a/uncore/src/uncore.scala b/uncore/src/uncore.scala index 8d1d396d..e3ebbc07 100644 --- a/uncore/src/uncore.scala +++ b/uncore/src/uncore.scala @@ -105,14 +105,9 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex val probe_initial_flags = Bits(width = conf.ln.nTiles) probe_initial_flags := Bits(0) if (conf.ln.nTiles > 1) { - // issue self-probes for uncached read xacts to facilitate I$ coherence - // TODO: this is hackish; figure out how to do it more systematically - val probe_self = co match { - case u: CoherencePolicyWithUncached => u.isUncachedReadTransaction(io.alloc_req.bits.acquire) - case _ => Bool(false) - } - val myflag = Mux(probe_self, Bits(0), UFixToOH(io.alloc_req.bits.client_id(log2Up(conf.ln.nTiles)-1,0))) - probe_initial_flags := ~(io.tile_incoherent | myflag) + val probe_self = co.needsSelfProbe(io.alloc_req.bits.acquire) + val probe_self_flag = Mux(probe_self, Bits(0), UFixToOH(io.alloc_req.bits.client_id(log2Up(conf.ln.nTiles)-1,0))) + probe_initial_flags := ~(io.tile_incoherent | probe_self_flag) } io.busy := state != s_idle From 319b4544d757f871a9fcd6437abf62847eeab179 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 28 Feb 2013 21:03:56 -0800 Subject: [PATCH 6/7] nTiles -> nClients in LogicalNetworkConfig --- uncore/src/package.scala | 2 +- uncore/src/uncore.scala | 116 +++++++++++++++++++-------------------- 2 files changed, 59 insertions(+), 59 deletions(-) diff --git a/uncore/src/package.scala b/uncore/src/package.scala index 8e511663..7cce3ff3 100644 --- a/uncore/src/package.scala +++ b/uncore/src/package.scala @@ -48,7 +48,7 @@ class BasicCrossbar[T <: Data]()(data: => T)(implicit conf: PhysicalNetworkConfi } } -case class LogicalNetworkConfiguration(nEndpoints: Int, idBits: Int, nHubs: Int, nTiles: Int) +case class LogicalNetworkConfiguration(nEndpoints: Int, idBits: Int, nMasters: Int, nClients: Int) abstract class LogicalNetwork[TileLinkType <: Bundle](endpoints: Seq[CoherenceAgentRole])(implicit conf: LogicalNetworkConfiguration) extends Component { val io: Vec[TileLinkType] diff --git a/uncore/src/uncore.scala b/uncore/src/uncore.scala index e3ebbc07..5609b701 100644 --- a/uncore/src/uncore.scala +++ b/uncore/src/uncore.scala @@ -24,9 +24,9 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex val p_data = (new PipeIO) { new TrackerProbeData }.flip val can_alloc = Bool(INPUT) val grant_ack = Bool(INPUT) - val release_cnt_dec = Bits(INPUT, conf.ln.nTiles) - val probe_cnt_inc = Bits(INPUT, conf.ln.nTiles) - val tile_incoherent = Bits(INPUT, conf.ln.nTiles) + val release_cnt_dec = Bits(INPUT, conf.ln.nClients) + val probe_cnt_inc = Bits(INPUT, conf.ln.nClients) + val tile_incoherent = Bits(INPUT, conf.ln.nClients) val release_data = (new PipeIO) { new ReleaseData }.flip val acquire_data = (new PipeIO) { new AcquireData }.flip val sent_grant_ack = Bool(INPUT) @@ -44,13 +44,13 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex val client_xact_id = Bits(OUTPUT, CLIENT_XACT_ID_BITS) val sharer_count = Bits(OUTPUT, conf.ln.idBits+1) val a_type = Bits(OUTPUT, ACQUIRE_TYPE_MAX_BITS) - val push_probe = Bits(OUTPUT, conf.ln.nTiles) - val pop_release = Bits(OUTPUT, conf.ln.nTiles) - val pop_release_data = Bits(OUTPUT, conf.ln.nTiles) - val pop_release_dep = Bits(OUTPUT, conf.ln.nTiles) - val pop_acquire = Bits(OUTPUT, conf.ln.nTiles) - val pop_acquire_data = Bits(OUTPUT, conf.ln.nTiles) - val pop_acquire_dep = Bits(OUTPUT, conf.ln.nTiles) + val push_probe = Bits(OUTPUT, conf.ln.nClients) + val pop_release = Bits(OUTPUT, conf.ln.nClients) + val pop_release_data = Bits(OUTPUT, conf.ln.nClients) + val pop_release_dep = Bits(OUTPUT, conf.ln.nClients) + val pop_acquire = Bits(OUTPUT, conf.ln.nClients) + val pop_acquire_data = Bits(OUTPUT, conf.ln.nClients) + val pop_acquire_dep = Bits(OUTPUT, conf.ln.nClients) val send_grant_ack = Bool(OUTPUT) } @@ -91,8 +91,8 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex val state = Reg(resetVal = s_idle) val xact = Reg{ new Acquire } val init_client_id_ = Reg{ Bits() } - val release_count = if (conf.ln.nTiles == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles))) - val probe_flags = Reg(resetVal = Bits(0, width = conf.ln.nTiles)) + val release_count = if (conf.ln.nClients == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2Up(conf.ln.nClients))) + val probe_flags = Reg(resetVal = Bits(0, width = conf.ln.nClients)) val release_client_id_ = Reg{ Bits() } val x_needs_read = Reg(resetVal = Bool(false)) val acquire_data_needs_write = Reg(resetVal = Bool(false)) @@ -102,11 +102,11 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex val mem_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES))) val mem_cnt_next = mem_cnt + UFix(1) val mem_cnt_max = ~UFix(0, width = log2Up(REFILL_CYCLES)) - val probe_initial_flags = Bits(width = conf.ln.nTiles) + val probe_initial_flags = Bits(width = conf.ln.nClients) probe_initial_flags := Bits(0) - if (conf.ln.nTiles > 1) { + if (conf.ln.nClients > 1) { val probe_self = co.needsSelfProbe(io.alloc_req.bits.acquire) - val probe_self_flag = Mux(probe_self, Bits(0), UFixToOH(io.alloc_req.bits.client_id(log2Up(conf.ln.nTiles)-1,0))) + val probe_self_flag = Mux(probe_self, Bits(0), UFixToOH(io.alloc_req.bits.client_id(log2Up(conf.ln.nClients)-1,0))) probe_initial_flags := ~(io.tile_incoherent | probe_self_flag) } @@ -115,7 +115,7 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex io.init_client_id := init_client_id_ io.release_client_id := release_client_id_ io.client_xact_id := xact.client_xact_id - io.sharer_count := UFix(conf.ln.nTiles) // TODO: Broadcast only + io.sharer_count := UFix(conf.ln.nClients) // TODO: Broadcast only io.a_type := xact.a_type io.mem_req_cmd.valid := Bool(false) @@ -129,13 +129,13 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex io.probe.bits.p_type := co.getProbeType(xact.a_type, UFix(0)) io.probe.bits.master_xact_id := UFix(id) io.probe.bits.addr := xact.addr - io.push_probe := Bits(0, width = conf.ln.nTiles) - io.pop_release := Bits(0, width = conf.ln.nTiles) - io.pop_release_data := Bits(0, width = conf.ln.nTiles) - io.pop_release_dep := Bits(0, width = conf.ln.nTiles) - io.pop_acquire := Bits(0, width = conf.ln.nTiles) - io.pop_acquire_data := Bits(0, width = conf.ln.nTiles) - io.pop_acquire_dep := Bits(0, width = conf.ln.nTiles) + io.push_probe := Bits(0, width = conf.ln.nClients) + io.pop_release := Bits(0, width = conf.ln.nClients) + io.pop_release_data := Bits(0, width = conf.ln.nClients) + io.pop_release_dep := Bits(0, width = conf.ln.nClients) + io.pop_acquire := Bits(0, width = conf.ln.nClients) + io.pop_acquire_data := Bits(0, width = conf.ln.nClients) + io.pop_acquire_dep := Bits(0, width = conf.ln.nClients) io.send_grant_ack := Bool(false) switch (state) { @@ -150,7 +150,7 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex p_w_mem_cmd_sent := Bool(false) x_w_mem_cmd_sent := Bool(false) io.pop_acquire := UFix(1) << io.alloc_req.bits.client_id - if(conf.ln.nTiles > 1) { + if(conf.ln.nClients > 1) { release_count := PopCount(probe_initial_flags) state := Mux(probe_initial_flags.orR, s_probe, s_mem) } else state := s_mem @@ -167,7 +167,7 @@ class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) ex when(io.release_cnt_dec.orR) { val dec = PopCount(io.release_cnt_dec) io.pop_release := io.release_cnt_dec - if(conf.ln.nTiles > 1) release_count := release_count - dec + if(conf.ln.nClients > 1) release_count := release_count - dec when(release_count === dec) { state := s_mem } @@ -223,7 +223,7 @@ case class CoherenceHubConfiguration(co: CoherencePolicy, ln: LogicalNetworkConf class CoherenceHubAdapter(implicit conf: LogicalNetworkConfiguration) extends Component with MasterCoherenceAgent { val io = new Bundle { val net = (new TileLinkIO).flip - val hub = Vec(conf.nTiles) { new TileLinkIO } + val hub = Vec(conf.nClients) { new TileLinkIO } } val netClientProducedSubBundles = io.net.getClass.getMethods.filter( x => @@ -259,8 +259,8 @@ class CoherenceHubAdapter(implicit conf: LogicalNetworkConfiguration) extends Co abstract class CoherenceHub(implicit conf: LogicalNetworkConfiguration) extends Component with MasterCoherenceAgent { val io = new Bundle { - val tiles = Vec(conf.nTiles) { new TileLinkIO }.flip - val incoherent = Vec(conf.nTiles) { Bool() }.asInput + val tiles = Vec(conf.nClients) { new TileLinkIO }.flip + val incoherent = Vec(conf.nClients) { Bool() }.asInput val mem = new ioMem } } @@ -307,8 +307,8 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co val send_grant_ack_arr = Vec(NGLOBAL_XACTS){ Bool() } val do_free_arr = Vec(NGLOBAL_XACTS){ Bool() } - val release_cnt_dec_arr = VecBuf(NGLOBAL_XACTS){ Vec(conf.ln.nTiles){ Bool()} } - val probe_cnt_inc_arr = VecBuf(NGLOBAL_XACTS){ Vec(conf.ln.nTiles){ Bool()} } + val release_cnt_dec_arr = VecBuf(NGLOBAL_XACTS){ Vec(conf.ln.nClients){ Bool()} } + val probe_cnt_inc_arr = VecBuf(NGLOBAL_XACTS){ Vec(conf.ln.nClients){ Bool()} } val sent_grant_ack_arr = Vec(NGLOBAL_XACTS){ Bool() } val p_data_client_id_arr = Vec(NGLOBAL_XACTS){ Bits(width=conf.ln.idBits) } val p_data_valid_arr = Vec(NGLOBAL_XACTS){ Bool() } @@ -333,17 +333,17 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co sent_grant_ack_arr(i) := Bool(false) p_data_client_id_arr(i) := Bits(0, width = conf.ln.idBits) p_data_valid_arr(i) := Bool(false) - for( j <- 0 until conf.ln.nTiles) { + for( j <- 0 until conf.ln.nClients) { release_cnt_dec_arr(i)(j) := Bool(false) probe_cnt_inc_arr(i)(j) := Bool(false) } } - val release_data_dep_list = List.fill(conf.ln.nTiles)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth must >= NPRIMARY - val acquire_data_dep_list = List.fill(conf.ln.nTiles)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth should >= NPRIMARY + val release_data_dep_list = List.fill(conf.ln.nClients)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth must >= NPRIMARY + val acquire_data_dep_list = List.fill(conf.ln.nClients)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth should >= NPRIMARY // Free finished transactions - for( j <- 0 until conf.ln.nTiles ) { + for( j <- 0 until conf.ln.nClients ) { val ack = io.tiles(j).grant_ack when (ack.valid) { do_free_arr(ack.bits.payload.master_xact_id) := Bool(true) @@ -355,7 +355,7 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co // Forward memory responses from mem to tile or arbitrate to ack val mem_idx = io.mem.resp.bits.tag val ack_idx = PriorityEncoder(send_grant_ack_arr.toBits) - for( j <- 0 until conf.ln.nTiles ) { + for( j <- 0 until conf.ln.nClients ) { val rep = io.tiles(j).grant rep.bits.payload.g_type := UFix(0) rep.bits.payload.client_xact_id := UFix(0) @@ -393,7 +393,7 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co io.mem.req_data <> Queue(mem_req_data_arb.io.out) // Handle probe replies, which may or may not have data - for( j <- 0 until conf.ln.nTiles ) { + for( j <- 0 until conf.ln.nClients ) { val release = io.tiles(j).release val release_data = io.tiles(j).release_data val idx = release.bits.payload.master_xact_id @@ -413,10 +413,10 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co trackerList(i).io.release_data.valid := io.tiles(trackerList(i).io.release_client_id).release_data.valid trackerList(i).io.release_data.bits := io.tiles(trackerList(i).io.release_client_id).release_data.bits.payload - trackerList(i).io.release_data_dep.valid := MuxLookup(trackerList(i).io.release_client_id, release_data_dep_list(0).io.deq.valid, (0 until conf.ln.nTiles).map( j => UFix(j) -> release_data_dep_list(j).io.deq.valid)) - trackerList(i).io.release_data_dep.bits := MuxLookup(trackerList(i).io.release_client_id, release_data_dep_list(0).io.deq.bits, (0 until conf.ln.nTiles).map( j => UFix(j) -> release_data_dep_list(j).io.deq.bits)) + trackerList(i).io.release_data_dep.valid := MuxLookup(trackerList(i).io.release_client_id, release_data_dep_list(0).io.deq.valid, (0 until conf.ln.nClients).map( j => UFix(j) -> release_data_dep_list(j).io.deq.valid)) + trackerList(i).io.release_data_dep.bits := MuxLookup(trackerList(i).io.release_client_id, release_data_dep_list(0).io.deq.bits, (0 until conf.ln.nClients).map( j => UFix(j) -> release_data_dep_list(j).io.deq.bits)) - for( j <- 0 until conf.ln.nTiles) { + for( j <- 0 until conf.ln.nClients) { val release = io.tiles(j).release release_cnt_dec_arr(i)(j) := release.valid && (release.bits.payload.master_xact_id === UFix(i)) } @@ -426,7 +426,7 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co // Only one allocation per cycle // Init requests may or may not have data val alloc_arb = (new Arbiter(NGLOBAL_XACTS)) { Bool() } - val init_arb = (new Arbiter(conf.ln.nTiles)) { new TrackerAllocReq } + val init_arb = (new Arbiter(conf.ln.nClients)) { new TrackerAllocReq } for( i <- 0 until NGLOBAL_XACTS ) { alloc_arb.io.in(i).valid := !trackerList(i).io.busy trackerList(i).io.can_alloc := alloc_arb.io.in(i).ready @@ -435,10 +435,10 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co trackerList(i).io.acquire_data.bits := io.tiles(trackerList(i).io.init_client_id).acquire_data.bits.payload trackerList(i).io.acquire_data.valid := io.tiles(trackerList(i).io.init_client_id).acquire_data.valid - trackerList(i).io.acquire_data_dep.bits := MuxLookup(trackerList(i).io.init_client_id, acquire_data_dep_list(0).io.deq.bits, (0 until conf.ln.nTiles).map( j => UFix(j) -> acquire_data_dep_list(j).io.deq.bits)) - trackerList(i).io.acquire_data_dep.valid := MuxLookup(trackerList(i).io.init_client_id, acquire_data_dep_list(0).io.deq.valid, (0 until conf.ln.nTiles).map( j => UFix(j) -> acquire_data_dep_list(j).io.deq.valid)) + trackerList(i).io.acquire_data_dep.bits := MuxLookup(trackerList(i).io.init_client_id, acquire_data_dep_list(0).io.deq.bits, (0 until conf.ln.nClients).map( j => UFix(j) -> acquire_data_dep_list(j).io.deq.bits)) + trackerList(i).io.acquire_data_dep.valid := MuxLookup(trackerList(i).io.init_client_id, acquire_data_dep_list(0).io.deq.valid, (0 until conf.ln.nClients).map( j => UFix(j) -> acquire_data_dep_list(j).io.deq.valid)) } - for( j <- 0 until conf.ln.nTiles ) { + for( j <- 0 until conf.ln.nClients ) { val acquire = io.tiles(j).acquire val acquire_data = io.tiles(j).acquire_data val acquire_data_dep = acquire_data_dep_list(j).io.deq @@ -457,8 +457,8 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co // Handle probe request generation // Must arbitrate for each request port - val probe_arb_arr = List.fill(conf.ln.nTiles)((new Arbiter(NGLOBAL_XACTS)) { new Probe() }) - for( j <- 0 until conf.ln.nTiles ) { + val probe_arb_arr = List.fill(conf.ln.nClients)((new Arbiter(NGLOBAL_XACTS)) { new Probe() }) + for( j <- 0 until conf.ln.nClients ) { for( i <- 0 until NGLOBAL_XACTS ) { val t = trackerList(i).io probe_arb_arr(j).io.in(i).bits := t.probe.bits @@ -473,7 +473,7 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co abstract class CoherenceAgent(implicit conf: LogicalNetworkConfiguration) extends Component with MasterCoherenceAgent { val io = new Bundle { val network = (new TileLinkIO).flip - val incoherent = Vec(conf.nTiles) { Bool() }.asInput + val incoherent = Vec(conf.nClients) { Bool() }.asInput val mem = new ioMem } } @@ -604,7 +604,7 @@ abstract class XactTracker(id: Int)(implicit conf: CoherenceHubConfiguration) ex val release = (new FIFOIO){(new LogicalNetworkIO) { new Release }}.flip val release_data = (new FIFOIO){(new LogicalNetworkIO) { new ReleaseData }}.flip val free = Bool(INPUT) - val tile_incoherent = Bits(INPUT, conf.ln.nTiles) + val tile_incoherent = Bits(INPUT, conf.ln.nClients) val release_data_dep = (new FIFOIO) { new TrackerDependency }.flip val acquire_data_dep = (new FIFOIO) { new TrackerDependency }.flip val mem_resp = (new FIFOIO) { new MemResp }.flip @@ -624,7 +624,7 @@ class WritebackTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extend val s_idle :: s_mem :: s_ack :: s_busy :: Nil = Enum(4){ UFix() } val state = Reg(resetVal = s_idle) val xact = Reg{ new Release } - val init_client_id_ = Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles))) + val init_client_id_ = Reg(resetVal = UFix(0, width = log2Up(conf.ln.nClients))) val release_data_needs_write = Reg(resetVal = Bool(false)) val mem_cmd_sent = Reg(resetVal = Bool(false)) @@ -688,27 +688,27 @@ class AcquireTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends val s_idle :: s_ack :: s_mem :: s_probe :: s_busy :: Nil = Enum(5){ UFix() } val state = Reg(resetVal = s_idle) val xact = Reg{ new Acquire } - val init_client_id_ = Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles))) + val init_client_id_ = Reg(resetVal = UFix(0, width = log2Up(conf.ln.nClients))) //TODO: Will need id reg for merged release xacts - val init_sharer_cnt_ = Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles))) + val init_sharer_cnt_ = Reg(resetVal = UFix(0, width = log2Up(conf.ln.nClients))) val grant_type = co.getGrantType(xact.a_type, init_sharer_cnt_) - val release_count = if (conf.ln.nTiles == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles))) - val probe_flags = Reg(resetVal = Bits(0, width = conf.ln.nTiles)) + val release_count = if (conf.ln.nClients == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2Up(conf.ln.nClients))) + val probe_flags = Reg(resetVal = Bits(0, width = conf.ln.nClients)) val x_needs_read = Reg(resetVal = Bool(false)) val acquire_data_needs_write = Reg(resetVal = Bool(false)) val release_data_needs_write = Reg(resetVal = Bool(false)) val x_w_mem_cmd_sent = Reg(resetVal = Bool(false)) val p_w_mem_cmd_sent = Reg(resetVal = Bool(false)) - val probe_initial_flags = Bits(width = conf.ln.nTiles) + val probe_initial_flags = Bits(width = conf.ln.nClients) probe_initial_flags := Bits(0) - if (conf.ln.nTiles > 1) { + if (conf.ln.nClients > 1) { // issue self-probes for uncached read xacts to facilitate I$ coherence // TODO: this is hackish; figure out how to do it more systematically val probe_self = co match { case u: CoherencePolicyWithUncached => u.isUncachedReadTransaction(io.acquire.bits.payload) case _ => Bool(false) } - val myflag = Mux(probe_self, Bits(0), UFixToOH(io.acquire.bits.header.src(log2Up(conf.ln.nTiles)-1,0))) + val myflag = Mux(probe_self, Bits(0), UFixToOH(io.acquire.bits.header.src(log2Up(conf.ln.nClients)-1,0))) probe_initial_flags := ~(io.tile_incoherent | myflag) } @@ -746,7 +746,7 @@ class AcquireTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends when( io.acquire.valid ) { xact := io.acquire.bits.payload init_client_id_ := io.acquire.bits.header.src - init_sharer_cnt_ := UFix(conf.ln.nTiles) // TODO: Broadcast only + init_sharer_cnt_ := UFix(conf.ln.nClients) // TODO: Broadcast only acquire_data_needs_write := co.messageHasData(io.acquire.bits.payload) x_needs_read := co.needsMemRead(io.acquire.bits.payload.a_type, UFix(0)) probe_flags := probe_initial_flags @@ -754,7 +754,7 @@ class AcquireTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends p_w_mem_cmd_sent := Bool(false) x_w_mem_cmd_sent := Bool(false) io.acquire.ready := Bool(true) - if(conf.ln.nTiles > 1) { + if(conf.ln.nClients > 1) { release_count := PopCount(probe_initial_flags) state := Mux(probe_initial_flags.orR, s_probe, s_mem) } else state := s_mem @@ -771,7 +771,7 @@ class AcquireTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends } when(io.release.valid) { io.release.ready := Bool(true) - if(conf.ln.nTiles > 1) release_count := release_count - UFix(1) + if(conf.ln.nClients > 1) release_count := release_count - UFix(1) when(release_count === UFix(1)) { state := s_mem } From c36b1dfa30290b5009925c719c99e243a7f6313a Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Wed, 20 Mar 2013 14:10:16 -0700 Subject: [PATCH 7/7] Cleaned up uncore and coherence interface. Removed defunct broadcast hub. Trait-ified tilelink bundle components. Added generalized mem arbiter. --- uncore/src/coherence.scala | 86 ++-- uncore/src/consts.scala | 6 +- uncore/src/package.scala | 10 +- uncore/src/tilelink.scala | 132 +++++- uncore/src/uncore.scala | 841 ++++++++----------------------------- 5 files changed, 345 insertions(+), 730 deletions(-) diff --git a/uncore/src/coherence.scala b/uncore/src/coherence.scala index f7a75afc..b4c4067f 100644 --- a/uncore/src/coherence.scala +++ b/uncore/src/coherence.scala @@ -34,9 +34,7 @@ abstract class CoherencePolicy { def getVoluntaryWriteback(addr: UFix, client_id: UFix, master_id: UFix): Release def newRelease (incoming: Probe, state: UFix, id: UFix): Release - def messageHasData (rel: Release): Bool - def messageHasData (acq: Acquire): Bool - def messageHasData (grant: Grant): Bool + def messageHasData (rel: SourcedMessage): Bool def messageUpdatesDataArray (reply: Grant): Bool def messageIsUncached(acq: Acquire): Bool @@ -46,8 +44,8 @@ abstract class CoherencePolicy { def getGrantType(a_type: UFix, count: UFix): Bits def getGrantType(rel: Release, count: UFix): Bits def getProbeType(a_type: UFix, global_state: UFix): UFix - def needsMemRead(a_type: UFix, global_state: UFix): Bool - def needsMemWrite(a_type: UFix, global_state: UFix): Bool + def needsOuterRead(a_type: UFix, global_state: UFix): Bool + def needsOuterWrite(a_type: UFix, global_state: UFix): Bool def needsAckReply(a_type: UFix, global_state: UFix): Bool def needsSelfProbe(acq: Acquire): Bool def requiresAck(grant: Grant): Bool @@ -72,13 +70,12 @@ abstract class IncoherentPolicy extends CoherencePolicy { // UNIMPLEMENTED def newStateOnProbe(incoming: Probe, state: UFix): Bits = state def newRelease (incoming: Probe, state: UFix, id: UFix): Release = Release( UFix(0), UFix(0), UFix(0), UFix(0)) - def messageHasData (rel: Release) = Bool(false) def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool = Bool(false) def getGrantType(a_type: UFix, count: UFix): Bits = Bits(0) def getGrantType(rel: Release, count: UFix): Bits = Bits(0) def getProbeType(a_type: UFix, global_state: UFix): UFix = UFix(0) - def needsMemRead(a_type: UFix, global_state: UFix): Bool = Bool(false) - def needsMemWrite(a_type: UFix, global_state: UFix): Bool = Bool(false) + def needsOuterRead(a_type: UFix, global_state: UFix): Bool = Bool(false) + def needsOuterWrite(a_type: UFix, global_state: UFix): Bool = Bool(false) def needsAckReply(a_type: UFix, global_state: UFix): Bool = Bool(false) def needsSelfProbe(acq: Acquire) = Bool(false) def requiresAck(grant: Grant) = Bool(true) @@ -134,8 +131,12 @@ class ThreeStateIncoherence extends IncoherentPolicy { def getReleaseTypeOnCacheControl(cmd: Bits): Bits = releaseVoluntaryInvalidateData // TODO def getReleaseTypeOnVoluntaryWriteback(): Bits = releaseVoluntaryInvalidateData - def messageHasData (acq: Acquire): Bool = uFixListContains(hasDataAcquireTypeList, acq.a_type) - def messageHasData (grant: Grant): Bool = uFixListContains(hasDataGrantTypeList, grant.g_type) + def messageHasData( msg: SourcedMessage ) = msg match { + case acq: Acquire => uFixListContains(hasDataAcquireTypeList, acq.a_type) + case grant: Grant => uFixListContains(hasDataGrantTypeList, grant.g_type) + case rel: Release => Bool(false) + case _ => Bool(false) + } def messageUpdatesDataArray (reply: Grant) = (reply.g_type === grantData) def messageIsUncached(acq: Acquire): Bool = uFixListContains(uncachedAcquireTypeList, acq.a_type) } @@ -221,9 +222,12 @@ class MICoherence extends CoherencePolicyWithUncached { Release( Mux(needsWriteback(state), with_data, without_data), incoming.addr, id, incoming.master_xact_id) } - def messageHasData (rel: Release): Bool = uFixListContains(hasDataReleaseTypeList, rel.r_type) - def messageHasData (acq: Acquire): Bool = uFixListContains(hasDataAcquireTypeList, acq.a_type) - def messageHasData (grant: Grant): Bool = uFixListContains(hasDataGrantTypeList, grant.g_type) + def messageHasData(msg: SourcedMessage) = msg match { + case acq: Acquire => uFixListContains(hasDataAcquireTypeList, acq.a_type) + case grant: Grant => uFixListContains(hasDataGrantTypeList, grant.g_type) + case rel: Release => uFixListContains(hasDataReleaseTypeList, rel.r_type) + case _ => Bool(false) + } def messageUpdatesDataArray (reply: Grant): Bool = { (reply.g_type === grantReadExclusive) } @@ -259,10 +263,10 @@ class MICoherence extends CoherencePolicyWithUncached { )) } - def needsMemRead(a_type: UFix, global_state: UFix): Bool = { + def needsOuterRead(a_type: UFix, global_state: UFix): Bool = { (a_type != acquireWriteUncached) } - def needsMemWrite(a_type: UFix, global_state: UFix): Bool = { + def needsOuterWrite(a_type: UFix, global_state: UFix): Bool = { (a_type === acquireWriteUncached) } def needsAckReply(a_type: UFix, global_state: UFix): Bool = { @@ -373,9 +377,12 @@ class MEICoherence extends CoherencePolicyWithUncached { Release( Mux(needsWriteback(state), with_data, without_data), incoming.addr, id, incoming.master_xact_id) } - def messageHasData (rel: Release): Bool = uFixListContains(hasDataReleaseTypeList, rel.r_type) - def messageHasData (acq: Acquire): Bool = uFixListContains(hasDataAcquireTypeList, acq.a_type) - def messageHasData (grant: Grant): Bool = uFixListContains(hasDataGrantTypeList, grant.g_type) + def messageHasData(msg: SourcedMessage) = msg match { + case acq: Acquire => uFixListContains(hasDataAcquireTypeList, acq.a_type) + case grant: Grant => uFixListContains(hasDataGrantTypeList, grant.g_type) + case rel: Release => uFixListContains(hasDataReleaseTypeList, rel.r_type) + case _ => Bool(false) + } def messageUpdatesDataArray (reply: Grant): Bool = { (reply.g_type === grantReadExclusive) } @@ -413,10 +420,10 @@ class MEICoherence extends CoherencePolicyWithUncached { )) } - def needsMemRead(a_type: UFix, global_state: UFix): Bool = { + def needsOuterRead(a_type: UFix, global_state: UFix): Bool = { (a_type != acquireWriteUncached) } - def needsMemWrite(a_type: UFix, global_state: UFix): Bool = { + def needsOuterWrite(a_type: UFix, global_state: UFix): Bool = { (a_type === acquireWriteUncached) } def needsAckReply(a_type: UFix, global_state: UFix): Bool = { @@ -534,9 +541,12 @@ class MSICoherence extends CoherencePolicyWithUncached { Release( Mux(needsWriteback(state), with_data, without_data), incoming.addr, id, incoming.master_xact_id) } - def messageHasData (rel: Release): Bool = uFixListContains(hasDataReleaseTypeList, rel.r_type) - def messageHasData (acq: Acquire): Bool = uFixListContains(hasDataAcquireTypeList, acq.a_type) - def messageHasData (grant: Grant): Bool = uFixListContains(hasDataGrantTypeList, grant.g_type) + def messageHasData(msg: SourcedMessage) = msg match { + case acq: Acquire => uFixListContains(hasDataAcquireTypeList, acq.a_type) + case grant: Grant => uFixListContains(hasDataGrantTypeList, grant.g_type) + case rel: Release => uFixListContains(hasDataReleaseTypeList, rel.r_type) + case _ => Bool(false) + } def messageUpdatesDataArray (reply: Grant): Bool = { (reply.g_type === grantReadShared || reply.g_type === grantReadExclusive) } @@ -571,10 +581,10 @@ class MSICoherence extends CoherencePolicyWithUncached { )) } - def needsMemRead(a_type: UFix, global_state: UFix): Bool = { + def needsOuterRead(a_type: UFix, global_state: UFix): Bool = { (a_type != acquireWriteUncached) } - def needsMemWrite(a_type: UFix, global_state: UFix): Bool = { + def needsOuterWrite(a_type: UFix, global_state: UFix): Bool = { (a_type === acquireWriteUncached) } def needsAckReply(a_type: UFix, global_state: UFix): Bool = { @@ -693,9 +703,12 @@ class MESICoherence extends CoherencePolicyWithUncached { Release( Mux(needsWriteback(state), with_data, without_data), incoming.addr, id, incoming.master_xact_id) } - def messageHasData (rel: Release): Bool = uFixListContains(hasDataReleaseTypeList, rel.r_type) - def messageHasData (acq: Acquire): Bool = uFixListContains(hasDataAcquireTypeList, acq.a_type) - def messageHasData (grant: Grant): Bool = uFixListContains(hasDataGrantTypeList, grant.g_type) + def messageHasData(msg: SourcedMessage) = msg match { + case acq: Acquire => uFixListContains(hasDataAcquireTypeList, acq.a_type) + case grant: Grant => uFixListContains(hasDataGrantTypeList, grant.g_type) + case rel: Release => uFixListContains(hasDataReleaseTypeList, rel.r_type) + case _ => Bool(false) + } def messageUpdatesDataArray (reply: Grant): Bool = { (reply.g_type === grantReadShared || reply.g_type === grantReadExclusive) } @@ -733,10 +746,10 @@ class MESICoherence extends CoherencePolicyWithUncached { )) } - def needsMemRead(a_type: UFix, global_state: UFix): Bool = { + def needsOuterRead(a_type: UFix, global_state: UFix): Bool = { (a_type != acquireWriteUncached) } - def needsMemWrite(a_type: UFix, global_state: UFix): Bool = { + def needsOuterWrite(a_type: UFix, global_state: UFix): Bool = { (a_type === acquireWriteUncached) } def needsAckReply(a_type: UFix, global_state: UFix): Bool = { @@ -871,9 +884,12 @@ class MigratoryCoherence extends CoherencePolicyWithUncached { Release( Mux(needsWriteback(state), with_data, without_data), incoming.addr, id, incoming.master_xact_id) } - def messageHasData (acq: Acquire): Bool = uFixListContains(hasDataAcquireTypeList, acq.a_type) - def messageHasData (rel: Release): Bool = uFixListContains(hasDataReleaseTypeList, rel.r_type) - def messageHasData (grant: Grant): Bool = uFixListContains(hasDataGrantTypeList, grant.g_type) + def messageHasData(msg: SourcedMessage) = msg match { + case acq: Acquire => uFixListContains(hasDataAcquireTypeList, acq.a_type) + case grant: Grant => uFixListContains(hasDataGrantTypeList, grant.g_type) + case rel: Release => uFixListContains(hasDataReleaseTypeList, rel.r_type) + case _ => Bool(false) + } def messageUpdatesDataArray (reply: Grant): Bool = { uFixListContains(List(grantReadShared, grantReadExclusive, grantReadMigratory), reply.g_type) } @@ -913,10 +929,10 @@ class MigratoryCoherence extends CoherencePolicyWithUncached { )) } - def needsMemRead(a_type: UFix, global_state: UFix): Bool = { + def needsOuterRead(a_type: UFix, global_state: UFix): Bool = { (a_type != acquireWriteUncached && a_type != acquireInvalidateOthers) } - def needsMemWrite(a_type: UFix, global_state: UFix): Bool = { + def needsOuterWrite(a_type: UFix, global_state: UFix): Bool = { (a_type === acquireWriteUncached || a_type === acquireWriteWordUncached || a_type === acquireAtomicUncached) } def needsAckReply(a_type: UFix, global_state: UFix): Bool = { diff --git a/uncore/src/consts.scala b/uncore/src/consts.scala index b515c1c8..d348e0ff 100644 --- a/uncore/src/consts.scala +++ b/uncore/src/consts.scala @@ -11,7 +11,7 @@ abstract trait CoherenceConfigConstants { trait UncoreConstants { val NGLOBAL_XACTS = 8 - val MASTER_XACT_ID_BITS = log2Up(NGLOBAL_XACTS) + val MASTER_XACT_ID_MAX_BITS = log2Up(NGLOBAL_XACTS) val CACHE_DATA_SIZE_IN_BYTES = 1 << 6 } @@ -29,7 +29,7 @@ trait TileLinkTypeConstants { trait TileLinkSizeConstants extends TileLinkTypeConstants { - val CLIENT_XACT_ID_BITS = 5 + val CLIENT_XACT_ID_MAX_BITS = 10 val ACQUIRE_WRITE_MASK_BITS = 6 val ACQUIRE_SUBWORD_ADDR_BITS = 3 val ACQUIRE_ATOMIC_OP_BITS = 4 @@ -72,7 +72,7 @@ trait MemoryInterfaceConstants extends UncoreConstants with TileLinkSizeConstants { - val MEM_TAG_BITS = max(CLIENT_XACT_ID_BITS, MASTER_XACT_ID_BITS) + val MEM_TAG_BITS = max(CLIENT_XACT_ID_MAX_BITS, MASTER_XACT_ID_MAX_BITS) val MEM_DATA_BITS = 128 val REFILL_CYCLES = CACHE_DATA_SIZE_IN_BYTES*8/MEM_DATA_BITS } diff --git a/uncore/src/package.scala b/uncore/src/package.scala index 7cce3ff3..492079cc 100644 --- a/uncore/src/package.scala +++ b/uncore/src/package.scala @@ -40,8 +40,6 @@ class BasicCrossbar[T <: Data]()(data: => T)(implicit conf: PhysicalNetworkConfi rdy := arb.ready && (in.bits.header.dst === UFix(i)) }} out <> rrarb.io.out - //out.bits.header.src := rrarb.io.chosen.toUFix - //out.bits.header.dst := UFix(i) }} for(i <- 0 until conf.nEndpoints) { io.in(i).ready := rdyVecs.map(r => r(i)).reduceLeft(_||_) @@ -62,21 +60,23 @@ class LogicalHeader(implicit conf: LogicalNetworkConfiguration) extends Bundle { } object FIFOedLogicalNetworkIOWrapper { - def apply[T <: Data](in: FIFOIO[T])(implicit conf: LogicalNetworkConfiguration) = { - val shim = (new FIFOedLogicalNetworkIOWrapper){ in.bits.clone } + def apply[T <: Data](in: FIFOIO[T], src: UFix = UFix(0), dst: UFix = UFix(0))(implicit conf: LogicalNetworkConfiguration) = { + val shim = (new FIFOedLogicalNetworkIOWrapper(src, dst)){ in.bits.clone } shim.io.in.valid := in.valid shim.io.in.bits := in.bits in.ready := shim.io.in.ready shim.io.out } } -class FIFOedLogicalNetworkIOWrapper[T <: Data]()(data: => T)(implicit lconf: LogicalNetworkConfiguration) extends Component { +class FIFOedLogicalNetworkIOWrapper[T <: Data](src: UFix, dst: UFix)(data: => T)(implicit lconf: LogicalNetworkConfiguration) extends Component { val io = new Bundle { val in = (new FIFOIO){ data }.flip val out = (new FIFOIO){(new LogicalNetworkIO){ data }} } io.out.valid := io.in.valid io.out.bits.payload := io.in.bits + io.out.bits.header.dst := dst + io.out.bits.header.src := src io.in.ready := io.out.ready } diff --git a/uncore/src/tilelink.scala b/uncore/src/tilelink.scala index 73bf8aff..c16f8c9b 100644 --- a/uncore/src/tilelink.scala +++ b/uncore/src/tilelink.scala @@ -3,20 +3,30 @@ package uncore import Chisel._ import Constants._ -class PhysicalAddress extends Bundle { +trait HasPhysicalAddress extends Bundle { val addr = UFix(width = PADDR_BITS - OFFSET_BITS) } -class MemData extends Bundle { +trait HasClientTransactionId extends Bundle { + val client_xact_id = Bits(width = CLIENT_XACT_ID_MAX_BITS) +} + +trait HasMasterTransactionId extends Bundle { + val master_xact_id = Bits(width = MASTER_XACT_ID_MAX_BITS) +} + +trait HasMemData extends Bundle { val data = Bits(width = MEM_DATA_BITS) } -class MemReqCmd extends PhysicalAddress { +class MemData extends Bundle with HasMemData + +class MemReqCmd extends Bundle with HasPhysicalAddress { val rw = Bool() val tag = Bits(width = MEM_TAG_BITS) } -class MemResp extends MemData { +class MemResp extends Bundle with HasMemData { val tag = Bits(width = MEM_TAG_BITS) } @@ -32,9 +42,12 @@ class ioMemPipe extends Bundle { val resp = (new PipeIO) { new MemResp() }.flip } -class Acquire extends PhysicalAddress { +trait SourcedMessage extends Bundle +trait ClientSourcedMessage extends SourcedMessage +trait MasterSourcedMessage extends SourcedMessage + +class Acquire extends ClientSourcedMessage with HasPhysicalAddress with HasClientTransactionId { val a_type = Bits(width = ACQUIRE_TYPE_MAX_BITS) - val client_xact_id = Bits(width = CLIENT_XACT_ID_BITS) val write_mask = Bits(width = ACQUIRE_WRITE_MASK_BITS) val subword_addr = Bits(width = ACQUIRE_SUBWORD_ADDR_BITS) val atomic_opcode = Bits(width = ACQUIRE_ATOMIC_OP_BITS) @@ -47,6 +60,9 @@ object Acquire acq.a_type := a_type acq.addr := addr acq.client_xact_id := client_xact_id + acq.write_mask := Bits(0, width = ACQUIRE_WRITE_MASK_BITS) + acq.subword_addr := Bits(0, width = ACQUIRE_SUBWORD_ADDR_BITS) + acq.atomic_opcode := Bits(0, width = ACQUIRE_ATOMIC_OP_BITS) acq } def apply(a_type: Bits, addr: UFix, client_xact_id: UFix, write_mask: Bits) = { @@ -55,6 +71,8 @@ object Acquire acq.addr := addr acq.client_xact_id := client_xact_id acq.write_mask := write_mask + acq.subword_addr := Bits(0, width = ACQUIRE_SUBWORD_ADDR_BITS) + acq.atomic_opcode := Bits(0, width = ACQUIRE_ATOMIC_OP_BITS) acq } def apply(a_type: Bits, addr: UFix, client_xact_id: UFix, subword_addr: UFix, atomic_opcode: UFix) = { @@ -64,15 +82,15 @@ object Acquire acq.client_xact_id := client_xact_id acq.subword_addr := subword_addr acq.atomic_opcode := atomic_opcode + acq.write_mask := Bits(0, width = ACQUIRE_WRITE_MASK_BITS) acq } } -class AcquireData extends MemData +class AcquireData extends ClientSourcedMessage with HasMemData -class Probe extends PhysicalAddress { +class Probe extends MasterSourcedMessage with HasPhysicalAddress with HasMasterTransactionId { val p_type = Bits(width = PROBE_TYPE_MAX_BITS) - val master_xact_id = Bits(width = MASTER_XACT_ID_BITS) } object Release @@ -86,35 +104,105 @@ object Release rel } } -class Release extends PhysicalAddress { +class Release extends ClientSourcedMessage with HasPhysicalAddress with HasClientTransactionId with HasMasterTransactionId { val r_type = Bits(width = RELEASE_TYPE_MAX_BITS) - val client_xact_id = Bits(width = CLIENT_XACT_ID_BITS) - val master_xact_id = Bits(width = MASTER_XACT_ID_BITS) } -class ReleaseData extends MemData +class ReleaseData extends ClientSourcedMessage with HasMemData -class Grant extends MemData { +class Grant extends MasterSourcedMessage with HasMemData with HasClientTransactionId with HasMasterTransactionId { val g_type = Bits(width = GRANT_TYPE_MAX_BITS) - val client_xact_id = Bits(width = CLIENT_XACT_ID_BITS) - val master_xact_id = Bits(width = MASTER_XACT_ID_BITS) } -class GrantAck extends Bundle { - val master_xact_id = Bits(width = MASTER_XACT_ID_BITS) -} +class GrantAck extends ClientSourcedMessage with HasMasterTransactionId abstract class DirectionalFIFOIO[T <: Data]()(data: => T) extends FIFOIO()(data) class ClientSourcedIO[T <: Data]()(data: => T) extends DirectionalFIFOIO()(data) class MasterSourcedIO[T <: Data]()(data: => T) extends DirectionalFIFOIO()(data) {flip()} -class TileLinkIO(implicit conf: LogicalNetworkConfiguration) extends Bundle { +class UncachedTileLinkIO(implicit conf: LogicalNetworkConfiguration) extends Bundle { val acquire = (new ClientSourcedIO){(new LogicalNetworkIO){new Acquire }} val acquire_data = (new ClientSourcedIO){(new LogicalNetworkIO){new AcquireData }} + val grant = (new MasterSourcedIO) {(new LogicalNetworkIO){new Grant }} + val grant_ack = (new ClientSourcedIO){(new LogicalNetworkIO){new GrantAck }} + override def clone = { new UncachedTileLinkIO().asInstanceOf[this.type] } +} + +class TileLinkIO(implicit conf: LogicalNetworkConfiguration) extends UncachedTileLinkIO()(conf) { val probe = (new MasterSourcedIO){(new LogicalNetworkIO){new Probe }} val release = (new ClientSourcedIO){(new LogicalNetworkIO){new Release }} val release_data = (new ClientSourcedIO){(new LogicalNetworkIO){new ReleaseData }} - val grant = (new MasterSourcedIO){(new LogicalNetworkIO){new Grant }} - val grant_ack = (new ClientSourcedIO){(new LogicalNetworkIO){new GrantAck }} override def clone = { new TileLinkIO().asInstanceOf[this.type] } } + +object UncachedTileLinkIOArbiterShim { + def apply[T <: HasClientTransactionId](in: ClientSourcedIO[LogicalNetworkIO[T]], id: Int, max: Int)(implicit lconf: LogicalNetworkConfiguration) = { + val shim = (new UncachedTileLinkIOArbiterShim(id, max)){in.bits.payload.clone} + shim.io.in <> in + shim.io.out + } +} +class UncachedTileLinkIOArbiterShim[T <: HasClientTransactionId](id: Int, max: Int)(data: => T)(implicit lconf: LogicalNetworkConfiguration) extends Component { + val io = new Bundle { + val in = (new ClientSourcedIO){(new LogicalNetworkIO){ data }}.flip + val out = (new ClientSourcedIO){(new LogicalNetworkIO){ data }} + } + io.out.bits := io.in.bits + io.out.bits.payload.client_xact_id := Cat(io.in.bits.payload.client_xact_id, UFix(id, log2Up(max))) + io.out.valid := io.in.valid + io.in.ready := io.out.ready +} + + +class UncachedTileLinkIOArbiter(n: Int)(implicit conf: LogicalNetworkConfiguration) extends Component { + val io = new Bundle { + val in = Vec(n) { new UncachedTileLinkIO }.flip + val out = new UncachedTileLinkIO + } + + val mem_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES))) + val mem_cnt_next = mem_cnt + UFix(1) + val locked = Reg(resetVal = Bool(false)) + val lock_idx = Reg(resetVal = UFix(n)) + + when(io.out.acquire_data.valid && io.out.acquire_data.ready) { + mem_cnt := mem_cnt_next + when(!locked) { + locked := Bool(true) + lock_idx := Vec(io.in.map{ in => in.acquire_data.ready && in.acquire_data.valid}){Bool()}.indexWhere{i: Bool => i} + } + when(mem_cnt_next === UFix(0)) { + locked := Bool(false) + } + } + + val acqd_grant = ArbiterCtrl(io.in.map(_.acquire_data.valid)) + (0 until n).map(i => io.in(i).acquire_data.ready := Mux(locked, UFix(i) === lock_idx, acqd_grant(i)) && io.out.acquire_data.ready) + var acqd_bits = io.in(n-1).acquire_data.bits + for (i <- n-2 to 0 by -1) { + acqd_bits = Mux(io.in(i).acquire_data.valid, io.in(i).acquire_data.bits, acqd_bits) + } + val locked_req = io.in(lock_idx).acquire_data + io.out.acquire_data.bits := Mux(locked, locked_req.bits, acqd_bits) + io.out.acquire_data.valid := Mux(locked, locked_req.valid, io.in.map(_.acquire_data.valid).reduce(_||_)) + + val acq_arb = (new Arbiter(n)){ (new LogicalNetworkIO){new Acquire} } + io.out.acquire <> acq_arb.io.out + io.in.map(_.acquire).zipWithIndex.map{ case(acq, id) => UncachedTileLinkIOArbiterShim(acq, id, n) }.zip(acq_arb.io.in).map{ case (req, arb) => req <> arb} + + val grant_ack_arb = (new Arbiter(n)){ (new LogicalNetworkIO){new GrantAck} } + io.out.grant_ack <> grant_ack_arb.io.out + grant_ack_arb.io.in zip io.in map { case (arb, req) => arb <> req.grant_ack } + + io.out.grant.ready := Bool(false) + for (i <- 0 until n) { + val tag = io.out.grant.bits.payload.client_xact_id + io.in(i).grant.valid := Bool(false) + when (tag(log2Up(n)-1,0) === UFix(i)) { + io.in(i).grant.valid := io.out.grant.valid + io.out.grant.ready := io.in(i).grant.ready + } + io.in(i).grant.bits := io.out.grant.bits + io.in(i).grant.bits.payload.client_xact_id := tag >> UFix(log2Up(n)) + } +} diff --git a/uncore/src/uncore.scala b/uncore/src/uncore.scala index 5609b701..14467f7b 100644 --- a/uncore/src/uncore.scala +++ b/uncore/src/uncore.scala @@ -3,688 +3,199 @@ package uncore import Chisel._ import Constants._ -class TrackerProbeData(implicit conf: CoherenceHubConfiguration) extends Bundle { +class TrackerProbeData(implicit conf: UncoreConfiguration) extends Bundle { val client_id = Bits(width = conf.ln.idBits) } -class TrackerAllocReq(implicit conf: CoherenceHubConfiguration) extends Bundle { +class TrackerAllocReq(implicit conf: UncoreConfiguration) extends Bundle { val acquire = new Acquire() val client_id = Bits(width = conf.ln.idBits) override def clone = { new TrackerAllocReq().asInstanceOf[this.type] } } class TrackerDependency extends Bundle { - val master_xact_id = Bits(width = MASTER_XACT_ID_BITS) + val master_xact_id = Bits(width = MASTER_XACT_ID_MAX_BITS) } -class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) extends Component { - val co = conf.co - val io = new Bundle { - val alloc_req = (new FIFOIO) { new TrackerAllocReq }.flip - val p_data = (new PipeIO) { new TrackerProbeData }.flip - val can_alloc = Bool(INPUT) - val grant_ack = Bool(INPUT) - val release_cnt_dec = Bits(INPUT, conf.ln.nClients) - val probe_cnt_inc = Bits(INPUT, conf.ln.nClients) - val tile_incoherent = Bits(INPUT, conf.ln.nClients) - val release_data = (new PipeIO) { new ReleaseData }.flip - val acquire_data = (new PipeIO) { new AcquireData }.flip - val sent_grant_ack = Bool(INPUT) - val release_data_dep = (new PipeIO) { new TrackerDependency }.flip - val acquire_data_dep = (new PipeIO) { new TrackerDependency }.flip - - val mem_req_cmd = (new FIFOIO) { new MemReqCmd } - val mem_req_data = (new FIFOIO) { new MemData } - val mem_req_lock = Bool(OUTPUT) - val probe = (new FIFOIO) { new Probe } - val busy = Bool(OUTPUT) - val addr = Bits(OUTPUT, PADDR_BITS - OFFSET_BITS) - val init_client_id = Bits(OUTPUT, conf.ln.idBits) - val release_client_id = Bits(OUTPUT, conf.ln.idBits) - val client_xact_id = Bits(OUTPUT, CLIENT_XACT_ID_BITS) - val sharer_count = Bits(OUTPUT, conf.ln.idBits+1) - val a_type = Bits(OUTPUT, ACQUIRE_TYPE_MAX_BITS) - val push_probe = Bits(OUTPUT, conf.ln.nClients) - val pop_release = Bits(OUTPUT, conf.ln.nClients) - val pop_release_data = Bits(OUTPUT, conf.ln.nClients) - val pop_release_dep = Bits(OUTPUT, conf.ln.nClients) - val pop_acquire = Bits(OUTPUT, conf.ln.nClients) - val pop_acquire_data = Bits(OUTPUT, conf.ln.nClients) - val pop_acquire_dep = Bits(OUTPUT, conf.ln.nClients) - val send_grant_ack = Bool(OUTPUT) - } - - def doMemReqWrite(req_cmd: FIFOIO[MemReqCmd], req_data: FIFOIO[MemData], lock: Bool, data: PipeIO[MemData], trigger: Bool, cmd_sent: Bool, pop_data: Bits, pop_dep: Bits, at_front_of_dep_queue: Bool, client_id: UFix) { - req_cmd.bits.rw := Bool(true) - req_data.bits := data.bits - when(req_cmd.ready && req_cmd.valid) { - cmd_sent := Bool(true) - } - when (at_front_of_dep_queue) { - req_cmd.valid := !cmd_sent && req_data.ready && data.valid - lock := data.valid || cmd_sent - when (req_cmd.ready || cmd_sent) { - req_data.valid := data.valid - when(req_data.ready) { - pop_data := UFix(1) << client_id - when (data.valid) { - mem_cnt := mem_cnt_next - when(mem_cnt === UFix(REFILL_CYCLES-1)) { - pop_dep := UFix(1) << client_id - trigger := Bool(false) - } - } - } - } - } - } - - def doMemReqRead(req_cmd: FIFOIO[MemReqCmd], trigger: Bool) { - req_cmd.valid := Bool(true) - req_cmd.bits.rw := Bool(false) - when(req_cmd.ready) { - trigger := Bool(false) - } - } - - val s_idle :: s_ack :: s_mem :: s_probe :: s_busy :: Nil = Enum(5){ UFix() } - val state = Reg(resetVal = s_idle) - val xact = Reg{ new Acquire } - val init_client_id_ = Reg{ Bits() } - val release_count = if (conf.ln.nClients == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2Up(conf.ln.nClients))) - val probe_flags = Reg(resetVal = Bits(0, width = conf.ln.nClients)) - val release_client_id_ = Reg{ Bits() } - val x_needs_read = Reg(resetVal = Bool(false)) - val acquire_data_needs_write = Reg(resetVal = Bool(false)) - val release_data_needs_write = Reg(resetVal = Bool(false)) - val x_w_mem_cmd_sent = Reg(resetVal = Bool(false)) - val p_w_mem_cmd_sent = Reg(resetVal = Bool(false)) - val mem_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES))) - val mem_cnt_next = mem_cnt + UFix(1) - val mem_cnt_max = ~UFix(0, width = log2Up(REFILL_CYCLES)) - val probe_initial_flags = Bits(width = conf.ln.nClients) - probe_initial_flags := Bits(0) - if (conf.ln.nClients > 1) { - val probe_self = co.needsSelfProbe(io.alloc_req.bits.acquire) - val probe_self_flag = Mux(probe_self, Bits(0), UFixToOH(io.alloc_req.bits.client_id(log2Up(conf.ln.nClients)-1,0))) - probe_initial_flags := ~(io.tile_incoherent | probe_self_flag) - } - - io.busy := state != s_idle - io.addr := xact.addr - io.init_client_id := init_client_id_ - io.release_client_id := release_client_id_ - io.client_xact_id := xact.client_xact_id - io.sharer_count := UFix(conf.ln.nClients) // TODO: Broadcast only - io.a_type := xact.a_type - - io.mem_req_cmd.valid := Bool(false) - io.mem_req_cmd.bits.rw := Bool(false) - io.mem_req_cmd.bits.addr := xact.addr - io.mem_req_cmd.bits.tag := UFix(id) - io.mem_req_data.valid := Bool(false) - io.mem_req_data.bits.data := UFix(0) - io.mem_req_lock := Bool(false) - io.probe.valid := Bool(false) - io.probe.bits.p_type := co.getProbeType(xact.a_type, UFix(0)) - io.probe.bits.master_xact_id := UFix(id) - io.probe.bits.addr := xact.addr - io.push_probe := Bits(0, width = conf.ln.nClients) - io.pop_release := Bits(0, width = conf.ln.nClients) - io.pop_release_data := Bits(0, width = conf.ln.nClients) - io.pop_release_dep := Bits(0, width = conf.ln.nClients) - io.pop_acquire := Bits(0, width = conf.ln.nClients) - io.pop_acquire_data := Bits(0, width = conf.ln.nClients) - io.pop_acquire_dep := Bits(0, width = conf.ln.nClients) - io.send_grant_ack := Bool(false) - - switch (state) { - is(s_idle) { - when( io.alloc_req.valid && io.can_alloc ) { - xact := io.alloc_req.bits.acquire - init_client_id_ := io.alloc_req.bits.client_id - acquire_data_needs_write := co.messageHasData(io.alloc_req.bits.acquire) - x_needs_read := co.needsMemRead(io.alloc_req.bits.acquire.a_type, UFix(0)) - probe_flags := probe_initial_flags - mem_cnt := UFix(0) - p_w_mem_cmd_sent := Bool(false) - x_w_mem_cmd_sent := Bool(false) - io.pop_acquire := UFix(1) << io.alloc_req.bits.client_id - if(conf.ln.nClients > 1) { - release_count := PopCount(probe_initial_flags) - state := Mux(probe_initial_flags.orR, s_probe, s_mem) - } else state := s_mem - } - } - is(s_probe) { - when(probe_flags.orR) { - io.push_probe := probe_flags - io.probe.valid := Bool(true) - } - when(io.probe_cnt_inc.orR) { - probe_flags := probe_flags & ~io.probe_cnt_inc // unflag sent reqs - } - when(io.release_cnt_dec.orR) { - val dec = PopCount(io.release_cnt_dec) - io.pop_release := io.release_cnt_dec - if(conf.ln.nClients > 1) release_count := release_count - dec - when(release_count === dec) { - state := s_mem - } - } - when(io.p_data.valid) { - release_data_needs_write := Bool(true) - release_client_id_ := io.p_data.bits.client_id - } - } - is(s_mem) { - when (release_data_needs_write) { - doMemReqWrite(io.mem_req_cmd, - io.mem_req_data, - io.mem_req_lock, - io.release_data, - release_data_needs_write, - p_w_mem_cmd_sent, - io.pop_release_data, - io.pop_release_dep, - io.release_data_dep.valid && (io.release_data_dep.bits.master_xact_id === UFix(id)), - release_client_id_) - } . elsewhen(acquire_data_needs_write) { - doMemReqWrite(io.mem_req_cmd, - io.mem_req_data, - io.mem_req_lock, - io.acquire_data, - acquire_data_needs_write, - x_w_mem_cmd_sent, - io.pop_acquire_data, - io.pop_acquire_dep, - io.acquire_data_dep.valid && (io.acquire_data_dep.bits.master_xact_id === UFix(id)), - init_client_id_) - } . elsewhen (x_needs_read) { - doMemReqRead(io.mem_req_cmd, x_needs_read) - } . otherwise { - state := Mux(co.needsAckReply(xact.a_type, UFix(0)), s_ack, s_busy) - } - } - is(s_ack) { - io.send_grant_ack := Bool(true) - when(io.sent_grant_ack) { state := s_busy } - } - is(s_busy) { // Nothing left to do but wait for transaction to complete - when (io.grant_ack) { - state := s_idle - } - } - } -} - -case class CoherenceHubConfiguration(co: CoherencePolicy, ln: LogicalNetworkConfiguration) - -class CoherenceHubAdapter(implicit conf: LogicalNetworkConfiguration) extends Component with MasterCoherenceAgent { - val io = new Bundle { - val net = (new TileLinkIO).flip - val hub = Vec(conf.nClients) { new TileLinkIO } - } - - val netClientProducedSubBundles = io.net.getClass.getMethods.filter( x => - classOf[ClientSourcedIO[Data]].isAssignableFrom(x.getReturnType)).map{ m => - m.invoke(io.net).asInstanceOf[ClientSourcedIO[LogicalNetworkIO[Data]]] } - val netMasterProducedSubBundles = io.net.getClass.getMethods.filter( x => - classOf[MasterSourcedIO[Data]].isAssignableFrom(x.getReturnType)).map{ m => - m.invoke(io.net).asInstanceOf[MasterSourcedIO[LogicalNetworkIO[Data]]] } - - val hubClientProducedSubBundles = io.hub.map{ io => { - io.getClass.getMethods.filter( x => - classOf[ClientSourcedIO[Data]].isAssignableFrom(x.getReturnType)).map{ m => - m.invoke(io).asInstanceOf[ClientSourcedIO[LogicalNetworkIO[Data]]] }}}.transpose - val hubMasterProducedSubBundles = io.hub.map{ io => { - io.getClass.getMethods.filter( x => - classOf[MasterSourcedIO[Data]].isAssignableFrom(x.getReturnType)).map{ m => - m.invoke(io).asInstanceOf[MasterSourcedIO[LogicalNetworkIO[Data]]] }}}.transpose - - hubMasterProducedSubBundles.zip(netMasterProducedSubBundles).foreach{ case(hub, net) => { - net.bits.header.src := UFix(0) - net.bits.header.dst := Vec(hub.map(_.valid)){Bool()}.indexWhere{s: Bool => s} - net.bits.payload := hub(0).bits.payload - net.valid := hub.map(_.valid).fold(Bool(false))(_||_) - hub.foreach( _.ready := net.ready) - }} - hubClientProducedSubBundles.zip(netClientProducedSubBundles).foreach{ case(hub, net) => { - hub.foreach(_.bits.header := net.bits.header) - hub.zipWithIndex.foreach{ case(h,i) => h.valid := (net.bits.header.src === UFix(i)) && net.valid } - hub.foreach(_.bits.payload := net.bits.payload) - net.ready := hub.map(_.ready).fold(Bool(false))(_||_) - }} -} - -abstract class CoherenceHub(implicit conf: LogicalNetworkConfiguration) extends Component with MasterCoherenceAgent { - val io = new Bundle { - val tiles = Vec(conf.nClients) { new TileLinkIO }.flip - val incoherent = Vec(conf.nClients) { Bool() }.asInput - val mem = new ioMem - } -} - -class CoherenceHubNull(implicit conf: CoherenceHubConfiguration) extends CoherenceHub()(conf.ln) -{ - val co = conf.co.asInstanceOf[ThreeStateIncoherence] - - val acquire = io.tiles(0).acquire - val is_write = acquire.bits.payload.a_type === co.acquireWriteback - acquire.ready := io.mem.req_cmd.ready && !(is_write && io.mem.resp.valid) //stall write req/resp to handle previous read resp - io.mem.req_cmd.valid := acquire.valid && !(is_write && io.mem.resp.valid) - io.mem.req_cmd.bits.rw := is_write - io.mem.req_cmd.bits.tag := acquire.bits.payload.client_xact_id - io.mem.req_cmd.bits.addr := acquire.bits.payload.addr - io.mem.req_data <> io.tiles(0).acquire_data - - val grant = io.tiles(0).grant - grant.bits.payload.g_type := Mux(io.mem.resp.valid, co.grantData, co.grantAck) - grant.bits.payload.client_xact_id := Mux(io.mem.resp.valid, io.mem.resp.bits.tag, acquire.bits.payload.client_xact_id) - grant.bits.payload.master_xact_id := UFix(0) // don't care - grant.bits.payload.data := io.mem.resp.bits.data - grant.valid := io.mem.resp.valid || acquire.valid && is_write && io.mem.req_cmd.ready - - io.tiles(0).grant_ack.ready := Bool(true) - io.tiles(0).probe.valid := Bool(false) - io.tiles(0).release.ready := Bool(true) - io.tiles(0).release_data.ready := Bool(true) -} - - -class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends CoherenceHub()(conf.ln) -{ - implicit val lnConf = conf.ln - val co = conf.co - val trackerList = (0 until NGLOBAL_XACTS).map(new XactTrackerBroadcast(_)) - - val busy_arr = Vec(NGLOBAL_XACTS){ Bool() } - val addr_arr = Vec(NGLOBAL_XACTS){ Bits(width=PADDR_BITS-OFFSET_BITS) } - val init_client_id_arr = Vec(NGLOBAL_XACTS){ Bits(width=conf.ln.idBits) } - val client_xact_id_arr = Vec(NGLOBAL_XACTS){ Bits(width=CLIENT_XACT_ID_BITS) } - val a_type_arr = Vec(NGLOBAL_XACTS){ Bits(width=ACQUIRE_TYPE_MAX_BITS) } - val sh_count_arr = Vec(NGLOBAL_XACTS){ Bits(width=conf.ln.idBits) } - val send_grant_ack_arr = Vec(NGLOBAL_XACTS){ Bool() } - - val do_free_arr = Vec(NGLOBAL_XACTS){ Bool() } - val release_cnt_dec_arr = VecBuf(NGLOBAL_XACTS){ Vec(conf.ln.nClients){ Bool()} } - val probe_cnt_inc_arr = VecBuf(NGLOBAL_XACTS){ Vec(conf.ln.nClients){ Bool()} } - val sent_grant_ack_arr = Vec(NGLOBAL_XACTS){ Bool() } - val p_data_client_id_arr = Vec(NGLOBAL_XACTS){ Bits(width=conf.ln.idBits) } - val p_data_valid_arr = Vec(NGLOBAL_XACTS){ Bool() } - - for( i <- 0 until NGLOBAL_XACTS) { - val t = trackerList(i).io - busy_arr(i) := t.busy - addr_arr(i) := t.addr - init_client_id_arr(i) := t.init_client_id - client_xact_id_arr(i) := t.client_xact_id - a_type_arr(i) := t.a_type - sh_count_arr(i) := t.sharer_count - send_grant_ack_arr(i) := t.send_grant_ack - t.grant_ack := do_free_arr(i) - t.p_data.bits.client_id := p_data_client_id_arr(i) - t.p_data.valid := p_data_valid_arr(i) - t.release_cnt_dec := release_cnt_dec_arr(i).toBits - t.probe_cnt_inc := probe_cnt_inc_arr(i).toBits - t.tile_incoherent := io.incoherent.toBits - t.sent_grant_ack := sent_grant_ack_arr(i) - do_free_arr(i) := Bool(false) - sent_grant_ack_arr(i) := Bool(false) - p_data_client_id_arr(i) := Bits(0, width = conf.ln.idBits) - p_data_valid_arr(i) := Bool(false) - for( j <- 0 until conf.ln.nClients) { - release_cnt_dec_arr(i)(j) := Bool(false) - probe_cnt_inc_arr(i)(j) := Bool(false) - } - } - - val release_data_dep_list = List.fill(conf.ln.nClients)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth must >= NPRIMARY - val acquire_data_dep_list = List.fill(conf.ln.nClients)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth should >= NPRIMARY - - // Free finished transactions - for( j <- 0 until conf.ln.nClients ) { - val ack = io.tiles(j).grant_ack - when (ack.valid) { - do_free_arr(ack.bits.payload.master_xact_id) := Bool(true) - } - ack.ready := Bool(true) - } - - // Reply to initial requestor - // Forward memory responses from mem to tile or arbitrate to ack - val mem_idx = io.mem.resp.bits.tag - val ack_idx = PriorityEncoder(send_grant_ack_arr.toBits) - for( j <- 0 until conf.ln.nClients ) { - val rep = io.tiles(j).grant - rep.bits.payload.g_type := UFix(0) - rep.bits.payload.client_xact_id := UFix(0) - rep.bits.payload.master_xact_id := UFix(0) - rep.bits.payload.data := io.mem.resp.bits.data - rep.valid := Bool(false) - when(io.mem.resp.valid && (UFix(j) === init_client_id_arr(mem_idx))) { - rep.bits.payload.g_type := co.getGrantType(a_type_arr(mem_idx), sh_count_arr(mem_idx)) - rep.bits.payload.client_xact_id := client_xact_id_arr(mem_idx) - rep.bits.payload.master_xact_id := mem_idx - rep.valid := Bool(true) - } . otherwise { - rep.bits.payload.g_type := co.getGrantType(a_type_arr(ack_idx), sh_count_arr(ack_idx)) - rep.bits.payload.client_xact_id := client_xact_id_arr(ack_idx) - rep.bits.payload.master_xact_id := ack_idx - when (UFix(j) === init_client_id_arr(ack_idx)) { - rep.valid := send_grant_ack_arr.toBits.orR - sent_grant_ack_arr(ack_idx) := rep.ready - } - } - } - io.mem.resp.ready := io.tiles(init_client_id_arr(mem_idx)).grant.ready - - // Create an arbiter for the one memory port - // We have to arbitrate between the different trackers' memory requests - // and once we have picked a request, get the right write data - val mem_req_cmd_arb = (new Arbiter(NGLOBAL_XACTS)) { new MemReqCmd() } - val mem_req_data_arb = (new LockingArbiter(NGLOBAL_XACTS)) { new MemData() } - for( i <- 0 until NGLOBAL_XACTS ) { - mem_req_cmd_arb.io.in(i) <> trackerList(i).io.mem_req_cmd - mem_req_data_arb.io.in(i) <> trackerList(i).io.mem_req_data - mem_req_data_arb.io.lock(i) <> trackerList(i).io.mem_req_lock - } - io.mem.req_cmd <> Queue(mem_req_cmd_arb.io.out) - io.mem.req_data <> Queue(mem_req_data_arb.io.out) - - // Handle probe replies, which may or may not have data - for( j <- 0 until conf.ln.nClients ) { - val release = io.tiles(j).release - val release_data = io.tiles(j).release_data - val idx = release.bits.payload.master_xact_id - val pop_releases = trackerList.map(_.io.pop_release(j).toBool) - val do_pop = foldR(pop_releases)(_ || _) - release.ready := Bool(true) - release_data_dep_list(j).io.enq.valid := release.valid && co.messageHasData(release.bits.payload) - release_data_dep_list(j).io.enq.bits.master_xact_id := release.bits.payload.master_xact_id - release_data.ready := foldR(trackerList.map(_.io.pop_release_data(j)))(_ || _) - when (release.valid && co.messageHasData(release.bits.payload)) { - p_data_valid_arr(idx) := Bool(true) - p_data_client_id_arr(idx) := UFix(j) - } - release_data_dep_list(j).io.deq.ready := foldR(trackerList.map(_.io.pop_release_dep(j).toBool))(_||_) - } - for( i <- 0 until NGLOBAL_XACTS ) { - trackerList(i).io.release_data.valid := io.tiles(trackerList(i).io.release_client_id).release_data.valid - trackerList(i).io.release_data.bits := io.tiles(trackerList(i).io.release_client_id).release_data.bits.payload - - trackerList(i).io.release_data_dep.valid := MuxLookup(trackerList(i).io.release_client_id, release_data_dep_list(0).io.deq.valid, (0 until conf.ln.nClients).map( j => UFix(j) -> release_data_dep_list(j).io.deq.valid)) - trackerList(i).io.release_data_dep.bits := MuxLookup(trackerList(i).io.release_client_id, release_data_dep_list(0).io.deq.bits, (0 until conf.ln.nClients).map( j => UFix(j) -> release_data_dep_list(j).io.deq.bits)) - - for( j <- 0 until conf.ln.nClients) { - val release = io.tiles(j).release - release_cnt_dec_arr(i)(j) := release.valid && (release.bits.payload.master_xact_id === UFix(i)) - } - } - - // Handle transaction initiation requests - // Only one allocation per cycle - // Init requests may or may not have data - val alloc_arb = (new Arbiter(NGLOBAL_XACTS)) { Bool() } - val init_arb = (new Arbiter(conf.ln.nClients)) { new TrackerAllocReq } - for( i <- 0 until NGLOBAL_XACTS ) { - alloc_arb.io.in(i).valid := !trackerList(i).io.busy - trackerList(i).io.can_alloc := alloc_arb.io.in(i).ready - trackerList(i).io.alloc_req.bits := init_arb.io.out.bits - trackerList(i).io.alloc_req.valid := init_arb.io.out.valid - - trackerList(i).io.acquire_data.bits := io.tiles(trackerList(i).io.init_client_id).acquire_data.bits.payload - trackerList(i).io.acquire_data.valid := io.tiles(trackerList(i).io.init_client_id).acquire_data.valid - trackerList(i).io.acquire_data_dep.bits := MuxLookup(trackerList(i).io.init_client_id, acquire_data_dep_list(0).io.deq.bits, (0 until conf.ln.nClients).map( j => UFix(j) -> acquire_data_dep_list(j).io.deq.bits)) - trackerList(i).io.acquire_data_dep.valid := MuxLookup(trackerList(i).io.init_client_id, acquire_data_dep_list(0).io.deq.valid, (0 until conf.ln.nClients).map( j => UFix(j) -> acquire_data_dep_list(j).io.deq.valid)) - } - for( j <- 0 until conf.ln.nClients ) { - val acquire = io.tiles(j).acquire - val acquire_data = io.tiles(j).acquire_data - val acquire_data_dep = acquire_data_dep_list(j).io.deq - init_arb.io.in(j).valid := acquire.valid - init_arb.io.in(j).bits.acquire := acquire.bits.payload - init_arb.io.in(j).bits.client_id := UFix(j) - val pop_acquires = trackerList.map(_.io.pop_acquire(j).toBool) - acquire.ready := foldR(pop_acquires)(_||_) - acquire_data_dep_list(j).io.enq.valid := acquire.ready && co.messageHasData(acquire.bits.payload) - acquire_data_dep_list(j).io.enq.bits.master_xact_id := OHToUFix(pop_acquires) - acquire_data.ready := foldR(trackerList.map(_.io.pop_acquire_data(j).toBool))(_||_) - acquire_data_dep.ready := foldR(trackerList.map(_.io.pop_acquire_dep(j).toBool))(_||_) - } - - alloc_arb.io.out.ready := init_arb.io.out.valid - - // Handle probe request generation - // Must arbitrate for each request port - val probe_arb_arr = List.fill(conf.ln.nClients)((new Arbiter(NGLOBAL_XACTS)) { new Probe() }) - for( j <- 0 until conf.ln.nClients ) { - for( i <- 0 until NGLOBAL_XACTS ) { - val t = trackerList(i).io - probe_arb_arr(j).io.in(i).bits := t.probe.bits - probe_arb_arr(j).io.in(i).valid := t.probe.valid && t.push_probe(j) - probe_cnt_inc_arr(i)(j) := probe_arb_arr(j).io.in(i).ready - } - FIFOedLogicalNetworkIOWrapper(probe_arb_arr(j).io.out) <> io.tiles(j).probe - } - -} +case class UncoreConfiguration(co: CoherencePolicyWithUncached, ln: LogicalNetworkConfiguration) abstract class CoherenceAgent(implicit conf: LogicalNetworkConfiguration) extends Component with MasterCoherenceAgent { val io = new Bundle { - val network = (new TileLinkIO).flip + val client = (new TileLinkIO).flip + val master = new UncachedTileLinkIO val incoherent = Vec(conf.nClients) { Bool() }.asInput - val mem = new ioMem } } -class L2CoherenceAgent(implicit conf: CoherenceHubConfiguration) extends CoherenceAgent()(conf.ln) +class L2CoherenceAgent(bankId: Int)(implicit conf: UncoreConfiguration) extends CoherenceAgent()(conf.ln) { implicit val lnConf = conf.ln val co = conf.co - val trackerList = new WritebackTracker(0) +: (1 to NGLOBAL_XACTS).map(new AcquireTracker(_)) + val trackerList = new WritebackTracker(0, bankId) +: (1 to NGLOBAL_XACTS).map(new AcquireTracker(_, bankId)) val release_data_dep_q = (new Queue(NGLOBAL_XACTS)){new TrackerDependency} // depth must >= NPRIMARY val acquire_data_dep_q = (new Queue(NGLOBAL_XACTS)){new TrackerDependency} // depth should >= NPRIMARY - for( i <- 0 to NGLOBAL_XACTS ) { - val t = trackerList(i) - t.io.tile_incoherent := io.incoherent.toBits - t.io.mem_resp.valid := io.mem.resp.valid && (io.mem.resp.bits.tag === UFix(i)) - t.io.mem_resp.bits := io.mem.resp.bits - } - io.mem.resp.ready := trackerList.map(_.io.mem_resp.ready).reduce(_||_) + trackerList.map(_.io.tile_incoherent := io.incoherent.toBits) // Handle transaction initiation requests // Only one allocation per cycle // Init requests may or may not have data - val acquire = io.network.acquire - val acquire_data = io.network.acquire_data - val x_dep_deq = acquire_data_dep_q.io.deq + val acquire = io.client.acquire + val acquire_data = io.client.acquire_data + val acq_dep_deq = acquire_data_dep_q.io.deq val any_acquire_conflict = trackerList.map(_.io.has_acquire_conflict).reduce(_||_) val all_busy = trackerList.map(_.io.busy).reduce(_&&_) - val alloc_arb = (new Arbiter(NGLOBAL_XACTS+1)) { Bool() } - for( i <- 0 to NGLOBAL_XACTS ) { + val alloc_arb = (new Arbiter(trackerList.size)) { Bool() } + for( i <- 0 until trackerList.size ) { alloc_arb.io.in(i).valid := !trackerList(i).io.busy - trackerList(i).io.acquire.bits := acquire.bits - trackerList(i).io.acquire.valid := acquire.valid && alloc_arb.io.in(i).ready + val t = trackerList(i).io.client + t.acquire.bits := acquire.bits + t.acquire.valid := acquire.valid && alloc_arb.io.in(i).ready - trackerList(i).io.acquire_data.bits := acquire_data.bits - trackerList(i).io.acquire_data.valid := acquire_data.valid - trackerList(i).io.acquire_data_dep.bits := x_dep_deq.bits - trackerList(i).io.acquire_data_dep.valid := x_dep_deq.valid + t.acquire_data.bits := acquire_data.bits + t.acquire_data.valid := acquire_data.valid + trackerList(i).io.acquire_data_dep.bits := acq_dep_deq.bits + trackerList(i).io.acquire_data_dep.valid := acq_dep_deq.valid } - acquire.ready := trackerList.map(_.io.acquire.ready).reduce(_||_) - acquire_data.ready := trackerList.map(_.io.acquire_data.ready).reduce(_||_) + acquire.ready := trackerList.map(_.io.client.acquire.ready).reduce(_||_) + acquire_data.ready := trackerList.map(_.io.client.acquire_data.ready).reduce(_||_) acquire_data_dep_q.io.enq.valid := acquire.ready && co.messageHasData(acquire.bits.payload) - acquire_data_dep_q.io.enq.bits.master_xact_id := OHToUFix(trackerList.map(_.io.acquire.ready)) - x_dep_deq.ready := trackerList.map(_.io.acquire_data_dep.ready).reduce(_||_) - + acquire_data_dep_q.io.enq.bits.master_xact_id := OHToUFix(trackerList.map(_.io.client.acquire.ready)) + acq_dep_deq.ready := trackerList.map(_.io.acquire_data_dep.ready).reduce(_||_) alloc_arb.io.out.ready := acquire.valid // Handle probe request generation - val probe_arb = (new Arbiter(NGLOBAL_XACTS+1)){(new LogicalNetworkIO){ new Probe }} - for( i <- 0 to NGLOBAL_XACTS ) { - val t = trackerList(i).io - probe_arb.io.in(i).bits := t.probe.bits - probe_arb.io.in(i).valid := t.probe.valid - t.probe.ready := probe_arb.io.in(i).ready - } - io.network.probe <> probe_arb.io.out + val probe_arb = (new Arbiter(trackerList.size)){(new LogicalNetworkIO){ new Probe }} + io.client.probe <> probe_arb.io.out + probe_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.client.probe } // Handle probe replies, which may or may not have data - val release = io.network.release - val release_data = io.network.release_data + val release = io.client.release + val release_data = io.client.release_data val voluntary = co.isVoluntary(release.bits.payload) val any_release_conflict = trackerList.tail.map(_.io.has_release_conflict).reduce(_||_) val conflict_idx = Vec(trackerList.map(_.io.has_release_conflict)){Bool()}.lastIndexWhere{b: Bool => b} val idx = Mux(voluntary, Mux(any_release_conflict, conflict_idx, UFix(0)), release.bits.payload.master_xact_id) - release.ready := trackerList.map(_.io.release.ready).reduce(_||_) - release_data.ready := trackerList.map(_.io.release_data.ready).reduce(_||_) + release.ready := trackerList.map(_.io.client.release.ready).reduce(_||_) + release_data.ready := trackerList.map(_.io.client.release_data.ready).reduce(_||_) release_data_dep_q.io.enq.valid := release.valid && co.messageHasData(release.bits.payload) release_data_dep_q.io.enq.bits.master_xact_id := idx release_data_dep_q.io.deq.ready := trackerList.map(_.io.release_data_dep.ready).reduce(_||_) - for( i <- 0 to NGLOBAL_XACTS ) { - trackerList(i).io.release_data.valid := release_data.valid - trackerList(i).io.release_data.bits := release_data.bits + for( i <- 0 until trackerList.size ) { + val t = trackerList(i).io.client + t.release.valid := release.valid && (idx === UFix(i)) + t.release.bits := release.bits + t.release_data.valid := release_data.valid + t.release_data.bits := release_data.bits trackerList(i).io.release_data_dep.valid := release_data_dep_q.io.deq.valid trackerList(i).io.release_data_dep.bits := release_data_dep_q.io.deq.bits - trackerList(i).io.release.valid := release.valid && (idx === UFix(i)) - trackerList(i).io.release.bits := release.bits } // Reply to initial requestor - // Forward memory responses from mem to tile or arbitrate to ack - val grant_arb = (new Arbiter(NGLOBAL_XACTS+1)){(new LogicalNetworkIO){ new Grant }} - for( i <- 0 to NGLOBAL_XACTS ) { - val t = trackerList(i).io - grant_arb.io.in(i).bits := t.grant.bits - grant_arb.io.in(i).valid := t.grant.valid - t.grant.ready := grant_arb.io.in(i).ready - } - io.network.grant.valid := grant_arb.io.out.valid - io.network.grant.bits := grant_arb.io.out.bits - grant_arb.io.out.ready := io.network.grant.ready - when(io.mem.resp.valid) { - io.network.grant.valid := Bool(true) - io.network.grant.bits := Vec(trackerList.map(_.io.grant.bits)){(new LogicalNetworkIO){new Grant}}(io.mem.resp.bits.tag) - for( i <- 0 to NGLOBAL_XACTS ) { - trackerList(i).io.grant.ready := (io.mem.resp.bits.tag === UFix(i)) && io.network.grant.ready - } - } + val grant_arb = (new Arbiter(trackerList.size)){(new LogicalNetworkIO){ new Grant }} + io.client.grant <> grant_arb.io.out + grant_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.client.grant } // Free finished transactions - val ack = io.network.grant_ack - for( i <- 0 to NGLOBAL_XACTS ) { - trackerList(i).io.free := ack.valid && (ack.bits.payload.master_xact_id === UFix(i)) - } + val ack = io.client.grant_ack + trackerList.map(_.io.client.grant_ack.valid := ack.valid) + trackerList.map(_.io.client.grant_ack.bits := ack.bits) ack.ready := Bool(true) // Create an arbiter for the one memory port - // We have to arbitrate between the different trackers' memory requests - // and once we have picked a request, get the right write data - val mem_req_cmd_arb = (new Arbiter(NGLOBAL_XACTS+1)) { new MemReqCmd() } - val mem_req_data_arb = (new LockingArbiter(NGLOBAL_XACTS+1)) { new MemData() } - for( i <- 0 to NGLOBAL_XACTS ) { - mem_req_cmd_arb.io.in(i) <> trackerList(i).io.mem_req_cmd - mem_req_data_arb.io.in(i) <> trackerList(i).io.mem_req_data - mem_req_data_arb.io.lock(i) <> trackerList(i).io.mem_req_lock - } - io.mem.req_cmd <> Queue(mem_req_cmd_arb.io.out) - io.mem.req_data <> Queue(mem_req_data_arb.io.out) + val outer_arb = new UncachedTileLinkIOArbiter(trackerList.size) + outer_arb.io.in zip trackerList map { case(arb, t) => arb <> t.io.master } + io.master <> outer_arb.io.out } -abstract class XactTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends Component with MemoryRequestGenerator { +abstract class XactTracker()(implicit conf: UncoreConfiguration) extends Component with OuterRequestGenerator { val co = conf.co implicit val ln = conf.ln val io = new Bundle { - val acquire = (new FIFOIO){(new LogicalNetworkIO) { new Acquire }}.flip - val acquire_data = (new FIFOIO){(new LogicalNetworkIO) { new AcquireData }}.flip - val release = (new FIFOIO){(new LogicalNetworkIO) { new Release }}.flip - val release_data = (new FIFOIO){(new LogicalNetworkIO) { new ReleaseData }}.flip - val free = Bool(INPUT) - val tile_incoherent = Bits(INPUT, conf.ln.nClients) - val release_data_dep = (new FIFOIO) { new TrackerDependency }.flip - val acquire_data_dep = (new FIFOIO) { new TrackerDependency }.flip - val mem_resp = (new FIFOIO) { new MemResp }.flip + val client = (new TileLinkIO).flip + val master = new UncachedTileLinkIO - val mem_req_cmd = (new FIFOIO) { new MemReqCmd } - val mem_req_data = (new FIFOIO) { new MemData } - val mem_req_lock = Bool(OUTPUT) - val probe = (new FIFOIO) {(new LogicalNetworkIO) { new Probe }} - val grant = (new FIFOIO) {(new LogicalNetworkIO) { new Grant }} - val busy = Bool(OUTPUT) - val has_acquire_conflict = Bool(OUTPUT) - val has_release_conflict = Bool(OUTPUT) + val tile_incoherent = Bits(INPUT, conf.ln.nClients) + val release_data_dep = (new FIFOIO) { new TrackerDependency }.flip + val acquire_data_dep = (new FIFOIO) { new TrackerDependency }.flip + + val busy = Bool(OUTPUT) + val has_acquire_conflict = Bool(OUTPUT) + val has_release_conflict = Bool(OUTPUT) } } -class WritebackTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends XactTracker(id)(conf) { +class WritebackTracker(trackerId: Int, bankId: Int)(implicit conf: UncoreConfiguration) extends XactTracker()(conf) { val s_idle :: s_mem :: s_ack :: s_busy :: Nil = Enum(4){ UFix() } val state = Reg(resetVal = s_idle) val xact = Reg{ new Release } val init_client_id_ = Reg(resetVal = UFix(0, width = log2Up(conf.ln.nClients))) val release_data_needs_write = Reg(resetVal = Bool(false)) val mem_cmd_sent = Reg(resetVal = Bool(false)) + val cmd_to_write = co.getUncachedWriteAcquire(xact.addr, UFix(trackerId)) + val cmd_to_read = co.getUncachedReadAcquire(xact.addr, UFix(trackerId)) - io.acquire.ready := Bool(false) - io.acquire_data.ready := Bool(false) io.acquire_data_dep.ready := Bool(false) - io.mem_resp.ready := Bool(false) - io.probe.valid := Bool(false) + io.release_data_dep.ready := Bool(false) io.busy := Bool(true) io.has_acquire_conflict := Bool(false) - io.has_release_conflict := co.isCoherenceConflict(xact.addr, io.release.bits.payload.addr) && (state != s_idle) + io.has_release_conflict := co.isCoherenceConflict(xact.addr, io.client.release.bits.payload.addr) && (state != s_idle) - io.mem_req_cmd.valid := Bool(false) - io.mem_req_cmd.bits.rw := Bool(false) - io.mem_req_cmd.bits.addr := xact.addr - io.mem_req_cmd.bits.tag := UFix(id) - io.mem_req_data.valid := Bool(false) - io.mem_req_data.bits.data := UFix(0) - io.mem_req_lock := Bool(false) - io.release.ready := Bool(false) - io.release_data.ready := Bool(false) - io.release_data_dep.ready := Bool(false) - io.grant.valid := Bool(false) - io.grant.bits.payload.g_type := co.getGrantType(xact, UFix(0)) - io.grant.bits.payload.client_xact_id := xact.client_xact_id - io.grant.bits.payload.master_xact_id := UFix(id) - io.grant.bits.header.dst := init_client_id_ + io.master.grant.ready := Bool(false) + io.master.acquire.valid := Bool(false) + io.master.acquire.bits.payload := cmd_to_write + //TODO io.master.acquire.bits.header.dst + io.master.acquire.bits.header.src := UFix(bankId) + io.master.acquire_data.valid := Bool(false) + io.master.acquire_data.bits.payload.data := UFix(0) + //TODO io.master.acquire_data.bits.header.dst + io.master.acquire_data.bits.header.src := UFix(bankId) + io.client.acquire.ready := Bool(false) + io.client.acquire_data.ready := Bool(false) + io.client.probe.valid := Bool(false) + io.client.release.ready := Bool(false) + io.client.release_data.ready := Bool(false) + io.client.grant.valid := Bool(false) + io.client.grant.bits.payload.g_type := co.getGrantType(xact, UFix(0)) + io.client.grant.bits.payload.client_xact_id := xact.client_xact_id + io.client.grant.bits.payload.master_xact_id := UFix(trackerId) + io.client.grant.bits.header.dst := init_client_id_ + io.client.grant.bits.header.src := UFix(bankId) + io.client.grant_ack.valid := Bool(false) switch (state) { is(s_idle) { - when( io.release.valid ) { - xact := io.release.bits.payload - init_client_id_ := io.release.bits.header.src - release_data_needs_write := co.messageHasData(io.release.bits.payload) + when( io.client.release.valid ) { + xact := io.client.release.bits.payload + init_client_id_ := io.client.release.bits.header.src + release_data_needs_write := co.messageHasData(io.client.release.bits.payload) mem_cnt := UFix(0) mem_cmd_sent := Bool(false) - io.release.ready := Bool(true) + io.client.release.ready := Bool(true) state := s_mem } } is(s_mem) { when (release_data_needs_write) { - doMemReqWrite(io.mem_req_cmd, - io.mem_req_data, - io.mem_req_lock, - io.release_data, + doOuterReqWrite(io.master.acquire, + io.master.acquire_data, + io.client.release_data, release_data_needs_write, mem_cmd_sent, io.release_data_dep.ready, - io.release_data_dep.valid && (io.release_data_dep.bits.master_xact_id === UFix(id))) + io.release_data_dep.valid && (io.release_data_dep.bits.master_xact_id === UFix(trackerId))) } . otherwise { state := s_ack } } is(s_ack) { - io.grant.valid := Bool(true) - when(io.grant.ready) { state := s_idle } + io.client.grant.valid := Bool(true) + when(io.client.grant.ready) { state := s_idle } } } } -class AcquireTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends XactTracker(id)(conf) { +class AcquireTracker(trackerId: Int, bankId: Int)(implicit conf: UncoreConfiguration) extends XactTracker()(conf) { val s_idle :: s_ack :: s_mem :: s_probe :: s_busy :: Nil = Enum(5){ UFix() } val state = Reg(resetVal = s_idle) val xact = Reg{ new Acquire } @@ -697,63 +208,65 @@ class AcquireTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends val x_needs_read = Reg(resetVal = Bool(false)) val acquire_data_needs_write = Reg(resetVal = Bool(false)) val release_data_needs_write = Reg(resetVal = Bool(false)) - val x_w_mem_cmd_sent = Reg(resetVal = Bool(false)) - val p_w_mem_cmd_sent = Reg(resetVal = Bool(false)) + val cmd_to_write = co.getUncachedWriteAcquire(xact.addr, UFix(trackerId)) + val cmd_to_read = co.getUncachedReadAcquire(xact.addr, UFix(trackerId)) + val a_w_mem_cmd_sent = Reg(resetVal = Bool(false)) + val r_w_mem_cmd_sent = Reg(resetVal = Bool(false)) val probe_initial_flags = Bits(width = conf.ln.nClients) probe_initial_flags := Bits(0) if (conf.ln.nClients > 1) { // issue self-probes for uncached read xacts to facilitate I$ coherence - // TODO: this is hackish; figure out how to do it more systematically - val probe_self = co match { - case u: CoherencePolicyWithUncached => u.isUncachedReadTransaction(io.acquire.bits.payload) - case _ => Bool(false) - } - val myflag = Mux(probe_self, Bits(0), UFixToOH(io.acquire.bits.header.src(log2Up(conf.ln.nClients)-1,0))) + val probe_self = co.needsSelfProbe(io.client.acquire.bits.payload) + val myflag = Mux(probe_self, Bits(0), UFixToOH(io.client.acquire.bits.header.src(log2Up(conf.ln.nClients)-1,0))) probe_initial_flags := ~(io.tile_incoherent | myflag) } io.busy := state != s_idle - io.has_acquire_conflict := co.isCoherenceConflict(xact.addr, io.acquire.bits.payload.addr) && (state != s_idle) - io.has_release_conflict := co.isCoherenceConflict(xact.addr, io.release.bits.payload.addr) && (state != s_idle) - io.mem_req_cmd.valid := Bool(false) - io.mem_req_cmd.bits.rw := Bool(false) - io.mem_req_cmd.bits.addr := xact.addr - io.mem_req_cmd.bits.tag := UFix(id) - io.mem_req_data.valid := Bool(false) - io.mem_req_data.bits.data := UFix(0) - io.mem_req_lock := Bool(false) - io.probe.valid := Bool(false) - io.probe.bits.payload.p_type := co.getProbeType(xact.a_type, UFix(0)) - io.probe.bits.payload.master_xact_id := UFix(id) - io.probe.bits.payload.addr := xact.addr - io.probe.bits.header.dst := UFix(0) - io.grant.bits.payload.data := io.mem_resp.bits.data - io.grant.bits.payload.g_type := grant_type - io.grant.bits.payload.client_xact_id := xact.client_xact_id - io.grant.bits.payload.master_xact_id := UFix(id) - io.grant.bits.header.dst := init_client_id_ - io.grant.valid := (io.mem_resp.valid && (UFix(id) === io.mem_resp.bits.tag)) - io.acquire.ready := Bool(false) - io.acquire_data.ready := Bool(false) + io.has_acquire_conflict := co.isCoherenceConflict(xact.addr, io.client.acquire.bits.payload.addr) && (state != s_idle) + io.has_release_conflict := co.isCoherenceConflict(xact.addr, io.client.release.bits.payload.addr) && (state != s_idle) + io.master.acquire.valid := Bool(false) + io.master.acquire.bits.payload := co.getUncachedReadAcquire(xact.addr, UFix(trackerId)) + //TODO io.master.acquire.bits.header.dst + io.master.acquire.bits.header.src := UFix(bankId) + io.master.acquire_data.valid := Bool(false) + io.master.acquire_data.bits.payload.data := UFix(0) + //TODO io.master.acquire_data.bits.header.dst + io.master.acquire_data.bits.header := UFix(bankId) + io.client.probe.valid := Bool(false) + io.client.probe.bits.payload.p_type := co.getProbeType(xact.a_type, UFix(0)) + io.client.probe.bits.payload.master_xact_id := UFix(trackerId) + io.client.probe.bits.payload.addr := xact.addr + io.client.probe.bits.header.dst := UFix(0) + io.client.probe.bits.header.src := UFix(bankId) + io.client.grant.bits.payload.data := io.master.grant.bits.payload.data + io.client.grant.bits.payload.g_type := grant_type + io.client.grant.bits.payload.client_xact_id := xact.client_xact_id + io.client.grant.bits.payload.master_xact_id := UFix(trackerId) + io.client.grant.bits.header.dst := init_client_id_ + io.client.grant.bits.header.src := UFix(bankId) + io.client.grant.valid := (io.master.grant.valid && (UFix(trackerId) === io.master.grant.bits.payload.client_xact_id)) + io.client.acquire.ready := Bool(false) + io.client.acquire_data.ready := Bool(false) io.acquire_data_dep.ready := Bool(false) - io.release.ready := Bool(false) - io.release_data.ready := Bool(false) + io.client.release.ready := Bool(false) + io.client.release_data.ready := Bool(false) io.release_data_dep.ready := Bool(false) - io.mem_resp.ready := io.grant.ready + io.master.grant.ready := io.client.grant.ready + io.client.grant_ack.valid := Bool(false) switch (state) { is(s_idle) { - when( io.acquire.valid ) { - xact := io.acquire.bits.payload - init_client_id_ := io.acquire.bits.header.src + when( io.client.acquire.valid ) { + xact := io.client.acquire.bits.payload + init_client_id_ := io.client.acquire.bits.header.src init_sharer_cnt_ := UFix(conf.ln.nClients) // TODO: Broadcast only - acquire_data_needs_write := co.messageHasData(io.acquire.bits.payload) - x_needs_read := co.needsMemRead(io.acquire.bits.payload.a_type, UFix(0)) + acquire_data_needs_write := co.messageHasData(io.client.acquire.bits.payload) + x_needs_read := co.needsOuterRead(io.client.acquire.bits.payload.a_type, UFix(0)) probe_flags := probe_initial_flags mem_cnt := UFix(0) - p_w_mem_cmd_sent := Bool(false) - x_w_mem_cmd_sent := Bool(false) - io.acquire.ready := Bool(true) + r_w_mem_cmd_sent := Bool(false) + a_w_mem_cmd_sent := Bool(false) + io.client.acquire.ready := Bool(true) if(conf.ln.nClients > 1) { release_count := PopCount(probe_initial_flags) state := Mux(probe_initial_flags.orR, s_probe, s_mem) @@ -763,78 +276,76 @@ class AcquireTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends is(s_probe) { val curr_p_id = PriorityEncoder(probe_flags) when(probe_flags.orR) { - io.probe.valid := Bool(true) - io.probe.bits.header.dst := curr_p_id + io.client.probe.valid := Bool(true) + io.client.probe.bits.header.dst := curr_p_id } - when(io.probe.ready) { + when(io.client.probe.ready) { probe_flags := probe_flags & ~(UFixToOH(curr_p_id)) } - when(io.release.valid) { - io.release.ready := Bool(true) + when(io.client.release.valid) { + io.client.release.ready := Bool(true) if(conf.ln.nClients > 1) release_count := release_count - UFix(1) when(release_count === UFix(1)) { state := s_mem } - release_data_needs_write := co.messageHasData(io.release.bits.payload) + release_data_needs_write := co.messageHasData(io.client.release.bits.payload) } } is(s_mem) { when (release_data_needs_write) { - doMemReqWrite(io.mem_req_cmd, - io.mem_req_data, - io.mem_req_lock, - io.release_data, + doOuterReqWrite(io.master.acquire, + io.master.acquire_data, + io.client.release_data, release_data_needs_write, - p_w_mem_cmd_sent, + r_w_mem_cmd_sent, io.release_data_dep.ready, - io.release_data_dep.valid && (io.release_data_dep.bits.master_xact_id === UFix(id))) + io.release_data_dep.valid && (io.release_data_dep.bits.master_xact_id === UFix(trackerId))) } . elsewhen(acquire_data_needs_write) { - doMemReqWrite(io.mem_req_cmd, - io.mem_req_data, - io.mem_req_lock, - io.acquire_data, + doOuterReqWrite(io.master.acquire, + io.master.acquire_data, + io.client.acquire_data, acquire_data_needs_write, - x_w_mem_cmd_sent, + a_w_mem_cmd_sent, io.acquire_data_dep.ready, - io.acquire_data_dep.valid && (io.acquire_data_dep.bits.master_xact_id === UFix(id))) + io.acquire_data_dep.valid && (io.acquire_data_dep.bits.master_xact_id === UFix(trackerId))) } . elsewhen (x_needs_read) { - doMemReqRead(io.mem_req_cmd, x_needs_read) + doOuterReqRead(io.master.acquire, x_needs_read) } . otherwise { state := Mux(co.needsAckReply(xact.a_type, UFix(0)), s_ack, - Mux(co.requiresAck(io.grant.bits.payload), s_busy, s_idle)) + Mux(co.requiresAck(io.client.grant.bits.payload), s_busy, s_idle)) } } is(s_ack) { - io.grant.valid := Bool(true) - when(io.grant.ready) { state := Mux(co.requiresAck(io.grant.bits.payload), s_busy, s_idle) } + io.client.grant.valid := Bool(true) + when(io.client.grant.ready) { state := Mux(co.requiresAck(io.client.grant.bits.payload), s_busy, s_idle) } } is(s_busy) { // Nothing left to do but wait for transaction to complete - when (io.free) { + when (io.client.grant_ack.valid && io.client.grant_ack.bits.payload.master_xact_id === UFix(trackerId)) { state := s_idle } } } } -trait MemoryRequestGenerator { +abstract trait OuterRequestGenerator { + val cmd_to_write: Acquire + val cmd_to_read: Acquire val mem_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES))) val mem_cnt_next = mem_cnt + UFix(1) - val mem_cnt_max = ~UFix(0, width = log2Up(REFILL_CYCLES)) - def doMemReqWrite[T <: Data](req_cmd: FIFOIO[MemReqCmd], req_data: FIFOIO[MemData], lock: Bool, data: FIFOIO[LogicalNetworkIO[T]], trigger: Bool, cmd_sent: Bool, pop_dep: Bool, at_front_of_dep_queue: Bool) { - req_cmd.bits.rw := Bool(true) - req_data.bits := data.bits.payload - when(req_cmd.ready && req_cmd.valid) { + def doOuterReqWrite[T <: Data](master_acq: FIFOIO[LogicalNetworkIO[Acquire]], master_acq_data: FIFOIO[LogicalNetworkIO[AcquireData]], client_data: FIFOIO[LogicalNetworkIO[T]], trigger: Bool, cmd_sent: Bool, pop_dep: Bool, at_front_of_dep_queue: Bool) { + master_acq.bits.payload := cmd_to_write + master_acq_data.bits.payload := client_data.bits.payload + when(master_acq.ready && master_acq.valid) { cmd_sent := Bool(true) } when (at_front_of_dep_queue) { - req_cmd.valid := !cmd_sent && req_data.ready && data.valid - lock := data.valid || cmd_sent - when (req_cmd.ready || cmd_sent) { - req_data.valid := data.valid - when(req_data.ready) { - data.ready:= Bool(true) - when (data.valid) { + master_acq.valid := !cmd_sent && master_acq_data.ready && client_data.valid + when (master_acq.ready || cmd_sent) { + master_acq_data.valid := client_data.valid + when(master_acq_data.ready) { + client_data.ready:= Bool(true) + when (client_data.valid) { mem_cnt := mem_cnt_next when(mem_cnt === UFix(REFILL_CYCLES-1)) { pop_dep := Bool(true) @@ -846,10 +357,10 @@ trait MemoryRequestGenerator { } } - def doMemReqRead(req_cmd: FIFOIO[MemReqCmd], trigger: Bool) { - req_cmd.valid := Bool(true) - req_cmd.bits.rw := Bool(false) - when(req_cmd.ready) { + def doOuterReqRead(master_acq: FIFOIO[LogicalNetworkIO[Acquire]], trigger: Bool) { + master_acq.valid := Bool(true) + master_acq.bits.payload := cmd_to_read + when(master_acq.ready) { trigger := Bool(false) } }