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Rocket Chip fixes in response to lowRISC team's comments

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* DMA frontend-backend communication tunneled over TileLink/AXI
 * Split MMIO and Mem requests in l1tol2net instead of in AXI interconnect
 * Don't make NIOMSHRs configurable. Fixed at 1.
 * Connect accelerator-internal CSRs into the CSR file
 * Make mtvec register configurable and writeable
This commit is contained in:
Howard Mao
2016-01-14 15:10:40 -08:00
parent 97640f099d
commit 06c3f9b655
7 changed files with 68 additions and 60 deletions
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10
src/main/scala/TestConfigs.scala
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@ -13,14 +13,14 @@ class WithGroundTest extends Config(
case TLKey("L1toL2") =>
TileLinkParameters(
coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
nCachingClients = site(NTiles),
nCachelessClients = site(NTiles) + (if (site(UseDma)) 2 else 1),
maxClientXacts = max(site(NMSHRs) + site(NIOMSHRs),
maxClientXacts = max(site(NMSHRs) + 1,
max(site(GroundTestMaxXacts),
if (site(UseDma)) 4 else 1)),
maxClientsPerPort = max(if (site(BuildRoCC).isEmpty) 1 else 2,
if (site(UseDma)) site(NDmaTransactors) else 1),
if (site(UseDma)) site(NDmaTransactors) + 1 else 1),
maxManagerXacts = site(NAcquireTransactors) + 2,
dataBits = site(CacheBlockBytes)*8)
case BuildTiles => {
@ -93,10 +93,6 @@ class WithDmaStreamTest extends Config(
case UseDma => true
case BuildGroundTest =>
(id: Int, p: Parameters) => Module(new DmaStreamTest()(p))
case DmaStreamLoopbackAddr => {
val addrMap = new AddrHashMap(site(GlobalAddrMap))
addrMap("devices:loopback").start
}
case DmaStreamTestSettings => DmaStreamTestConfig(
source = 0x10, dest = 0x28, len = 0x18,
size = site(StreamLoopbackWidth) / 8)