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Rocket Chip fixes in response to lowRISC team's comments

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* DMA frontend-backend communication tunneled over TileLink/AXI
 * Split MMIO and Mem requests in l1tol2net instead of in AXI interconnect
 * Don't make NIOMSHRs configurable. Fixed at 1.
 * Connect accelerator-internal CSRs into the CSR file
 * Make mtvec register configurable and writeable
This commit is contained in:
Howard Mao
2016-01-14 15:10:40 -08:00
parent 97640f099d
commit 06c3f9b655
7 changed files with 68 additions and 60 deletions
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30
src/main/scala/Configs.scala
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@ -28,7 +28,7 @@ class DefaultConfig extends Config (
new AddrMap(deviceTree +: csrs :+ scr)
}
def makeDeviceTree() = {
val addrMap = new AddrHashMap(site(GlobalAddrMap))
val addrMap = new AddrHashMap(site(GlobalAddrMap), site(MMIOBase))
val devices = site(GlobalDeviceSet)
val dt = new DeviceTreeGenerator
dt.beginNode("")
@ -75,6 +75,7 @@ class DefaultConfig extends Config (
case HtifKey => HtifParameters(
width = Dump("HTIF_WIDTH", 16),
nSCR = 64,
csrDataBits = site(XLen),
offsetBits = site(CacheBlockOffsetBits),
nCores = site(NTiles))
//Memory Parameters
@ -89,8 +90,8 @@ class DefaultConfig extends Config (
case MIFTagBits => // Bits needed at the L2 agent
log2Up(site(NAcquireTransactors)+2) +
// Bits added by NASTI interconnect
log2Up(site(NMemoryChannels) * site(NBanksPerMemoryChannel) +
(if (site(UseDma)) 2 else 1))
max(log2Up(site(NBanksPerMemoryChannel)),
(if (site(UseDma)) 3 else 2))
case MIFDataBits => 64
case MIFAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)
case MIFDataBeats => site(CacheBlockBytes) * 8 / site(MIFDataBits)
@ -132,7 +133,6 @@ class DefaultConfig extends Config (
case StoreDataQueueDepth => 17
case ReplayQueueDepth => 16
case NMSHRs => Knob("L1D_MSHRS")
case NIOMSHRs => 1
case LRSCCycles => 32
//L2 Memory System Params
case NAcquireTransactors => 7
@ -153,11 +153,12 @@ class DefaultConfig extends Config (
}
case BuildRoCC => Nil
case RoccNMemChannels => site(BuildRoCC).map(_.nMemChannels).foldLeft(0)(_ + _)
case RoccNCSRs => site(BuildRoCC).map(_.csrs.size).foldLeft(0)(_ + _)
case UseDma => false
case UseStreamLoopback => false
case NDmaTransactors => 3
case NDmaXacts => site(NDmaTransactors) * site(NTiles)
case NDmaClients => site(NTiles)
case NDmaXactsPerClient => site(NDmaTransactors)
//Rocket Core Constants
case FetchWidth => 1
case RetireWidth => 1
@ -179,6 +180,7 @@ class DefaultConfig extends Config (
case CoreInstBits => 32
case CoreDataBits => site(XLen)
case NCustomMRWCSRs => 0
case MtvecInit => BigInt(0x100)
//Uncore Paramters
case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients
@ -187,17 +189,17 @@ class DefaultConfig extends Config (
case TLKey("L1toL2") =>
TileLinkParameters(
coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
nCachingClients = site(NTiles),
nCachelessClients = (if (site(UseDma)) 2 else 1) +
site(NTiles) *
(1 + (if(site(BuildRoCC).isEmpty) 0
else site(RoccNMemChannels))),
maxClientXacts = max(site(NMSHRs) + site(NIOMSHRs),
maxClientXacts = max(site(NMSHRs) + 1,
max(if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts),
if (site(UseDma)) 4 else 1)),
maxClientsPerPort = max(if (site(BuildRoCC).isEmpty) 1 else 2,
if (site(UseDma)) site(NDmaTransactors) else 1),
if (site(UseDma)) site(NDmaTransactors) + 1 else 1),
maxManagerXacts = site(NAcquireTransactors) + 2,
dataBits = site(CacheBlockBytes)*8)
case TLKey("L2toMC") =>
@ -225,7 +227,6 @@ class DefaultConfig extends Config (
case GlobalAddrMap => {
val extraSize = site(ExternalIOStart) - site(MMIOBase)
AddrMap(
AddrMapEntry("mem", None, MemChannels(site(MMIOBase), site(NMemoryChannels), AddrMapConsts.RWX)),
AddrMapEntry("conf", None, MemSubmap(extraSize / 2, genCsrAddrMap)),
AddrMapEntry("devices", None, MemSubmap(extraSize / 2, site(GlobalDeviceSet).getAddrMap)),
AddrMapEntry("io", Some(site(ExternalIOStart)), MemSize(2 * site(MMIOBase), AddrMapConsts.RW)))
@ -235,6 +236,9 @@ class DefaultConfig extends Config (
if (site(UseStreamLoopback)) {
devset.addDevice("loopback", site(StreamLoopbackWidth) / 8, "stream")
}
if (site(UseDma)) {
devset.addDevice("dma", site(CacheBlockBytes), "dma")
}
devset
}
}},
@ -403,7 +407,9 @@ class WithDmaController extends Config(
RoccParameters(
opcodes = OpcodeSet.custom2,
generator = (p: Parameters) => Module(new DmaController()(p)),
useDma = true))
csrs = Seq.range(
DmaCtrlRegNumbers.CSR_BASE,
DmaCtrlRegNumbers.CSR_END)))
case RoccMaxTaggedMemXacts => 1
})
@ -414,7 +420,9 @@ class WithStreamLoopback extends Config(
case StreamLoopbackWidth => 64
})
class DmaControllerConfig extends Config(new WithDmaController ++ new DefaultL2Config)
class DmaControllerConfig extends Config(new WithDmaController ++ new WithStreamLoopback ++ new DefaultL2Config)
class DualCoreDmaControllerConfig extends Config(new With2Cores ++ new DmaControllerConfig)
class DmaControllerFPGAConfig extends Config(new WithDmaController ++ new WithStreamLoopback ++ new DefaultFPGAConfig)
class SmallL2Config extends Config(
new With2MemoryChannels ++ new With4BanksPerMemChannel ++