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debug: Fix race between resumereq and resumeack

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For an arbitrary DMI master on a fast clock running against a core
on a slow clock, there was a race between writing resumereq and
reading resumeack. When using JTAG DTM this does not occur in practice,
but clean it up for running simulations with FESVR and future DMI masters.
This commit is contained in:
Megan Wachs 2017-06-29 12:27:23 -07:00
parent 7dae3388e1
commit 0668f13d99
1 changed files with 5 additions and 3 deletions
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8
src/main/scala/uncore/devices/debug/Debug.scala
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@ -540,8 +540,10 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
DMSTATUSRdData.anyrunning := true.B DMSTATUSRdData.anyrunning := true.B
} }
DMSTATUSRdData.allresumeack := ~resumeReqRegs(selectedHartReg) val resumereq = io.innerCtrl.fire() && io.innerCtrl.bits.resumereq
DMSTATUSRdData.anyresumeack := ~resumeReqRegs(selectedHartReg)
DMSTATUSRdData.allresumeack := ~resumeReqRegs(selectedHartReg) && ~resumereq
DMSTATUSRdData.anyresumeack := ~resumeReqRegs(selectedHartReg) && ~resumereq
//TODO //TODO
DMSTATUSRdData.cfgstrvalid := false.B DMSTATUSRdData.cfgstrvalid := false.B
@ -710,7 +712,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
resumeReqRegs(component) := false.B resumeReqRegs(component) := false.B
} }
} }
when(io.innerCtrl.fire() && io.innerCtrl.bits.resumereq) { when(resumereq) {
resumeReqRegs(io.innerCtrl.bits.hartsel) := true.B resumeReqRegs(io.innerCtrl.bits.hartsel) := true.B
} }
} }