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Merge pull request #983 from freechipsproject/kill-paddrbits

Remove global fields PAddrBits and ResetVectorBits
This commit is contained in:
Henry Cook 2017-09-11 12:51:10 -07:00 committed by GitHub
commit 063ca0ed4a
15 changed files with 67 additions and 63 deletions

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@ -5,7 +5,6 @@ package freechips.rocketchip.coreplex
import Chisel._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.rocket.PAddrBits
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._

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@ -15,11 +15,9 @@ import freechips.rocketchip.util._
class BaseCoreplexConfig extends Config ((site, here, up) => {
// Tile parameters
case PAddrBits => 32
case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */
case ASIdBits => 0
case XLen => 64 // Applies to all cores
case ResetVectorBits => site(PAddrBits)
case MaxHartIdBits => log2Up(site(RocketTilesKey).size)
case BuildCore => (p: Parameters) => new Rocket()(p)
case RocketTilesKey => Nil // Will be added by partial configs found below

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@ -3,12 +3,9 @@
package freechips.rocketchip.coreplex
import Chisel._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.tile.ResetVectorBits
/** A single place for all tiles to find out the reset vector */
trait HasResetVectorWire {
implicit val p: Parameters
val resetVectorBits = p(ResetVectorBits)
def resetVectorBits: Int
val global_reset_vector = Wire(UInt(width = resetVectorBits))
}

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@ -101,14 +101,19 @@ trait HasRocketTilesModuleImp extends LazyMultiIOModuleImp
with HasResetVectorWire
with HasPeripheryDebugModuleImp {
val outer: HasRocketTiles
val rocket_tile_inputs = Wire(Vec(outer.nRocketTiles, new ClockedRocketTileInputs))
// TODO make this less gross and/or support tiles with differently sized reset vectors
def resetVectorBits: Int = outer.paddrBits
val rocket_tile_inputs = Wire(Vec(outer.nRocketTiles, new ClockedRocketTileInputs()(p.alterPartial {
case SharedMemoryTLEdge => outer.sharedMemoryTLEdge
})))
// Unconditionally wire up the non-diplomatic tile inputs
outer.rocket_tiles.map(_.module).zip(rocket_tile_inputs).foreach { case(tile, wire) =>
tile.clock := wire.clock
tile.reset := wire.reset
tile.io.hartid := wire.hartid
tile.io.resetVector := wire.resetVector
tile.io.reset_vector := wire.reset_vector
}
// Default values for tile inputs; may be overriden in other traits
@ -116,7 +121,7 @@ trait HasRocketTilesModuleImp extends LazyMultiIOModuleImp
wire.clock := clock
wire.reset := reset
wire.hartid := UInt(i)
wire.resetVector := global_reset_vector
wire.reset_vector := global_reset_vector
}
}

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@ -125,4 +125,5 @@ trait HasSystemBus extends HasInterruptBus {
val sbus = new SystemBus(sbusParams)
def sharedMemoryTLEdge: TLEdge = sbus.busView
def paddrBits: Int = sbus.busView.bundle.addressBits
}

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@ -81,5 +81,5 @@ trait HasPeripheryBootROM extends HasPeripheryBus {
trait HasPeripheryBootROMModuleImp extends LazyMultiIOModuleImp
with HasResetVectorWire {
val outer: HasPeripheryBootROM
global_reset_vector := UInt(outer.resetVector, width = resetVectorBits)
global_reset_vector := outer.resetVector.U
}

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@ -6,7 +6,7 @@ package freechips.rocketchip.groundtest
import Chisel._
import freechips.rocketchip.config.Config
import freechips.rocketchip.coreplex._
import freechips.rocketchip.rocket.{DCacheParams, PAddrBits}
import freechips.rocketchip.rocket.{DCacheParams}
import freechips.rocketchip.tile.{MaxHartIdBits, XLen}
/** Actual testing target Configs */
@ -21,7 +21,7 @@ class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) extends Config(
case GroundTestTilesKey => params.map { dcp => TraceGenParams(
dcache = Some(dcp),
wordBits = site(XLen),
addrBits = site(PAddrBits),
addrBits = 32,
addrBag = {
val nSets = 2
val nWays = 1

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@ -64,13 +64,12 @@ class Frontend(val icacheParams: ICacheParams, hartid: Int)(implicit p: Paramete
DisableMonitors { implicit p => icache.slaveNode.map { _ := slaveNode } }
}
class FrontendBundle(outer: Frontend) extends CoreBundle()(outer.p) {
class FrontendBundle(outer: Frontend) extends CoreBundle()(outer.p)
with HasExternallyDrivenTileConstants {
val cpu = new FrontendIO().flip
val ptw = new TLBPTWIO()
val tl_out = outer.masterNode.bundleOut
val tl_in = outer.slaveNode.bundleIn
val resetVector = UInt(INPUT, vaddrBitsExtended)
val hartid = UInt(INPUT, hartIdLen)
}
class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
@ -90,7 +89,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
val s1_pc = Reg(UInt(width=vaddrBitsExtended))
val s1_speculative = Reg(Bool())
val s2_valid = RegInit(false.B)
val s2_pc = RegInit(alignPC(io.resetVector))
val s2_pc = RegInit(t = UInt(width = vaddrBitsExtended), alignPC(io.reset_vector))
val s2_btb_resp_valid = if (usingBTB) Reg(Bool()) else false.B
val s2_btb_resp_bits = Reg(new BTBResp)
val s2_tlb_resp = Reg(tlb.io.resp)

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@ -12,8 +12,7 @@ import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends LazyModule
with HasCoreParameters {
class ScratchpadSlavePort(address: AddressSet, coreDataBytes: Int, usingAtomics: Boolean)(implicit p: Parameters) extends LazyModule {
val device = new SimpleDevice("dtim", Seq("sifive,dtim0"))
val node = TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters(
@ -97,23 +96,25 @@ class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends L
}
/** Mix-ins for constructing tiles that have optional scratchpads */
trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend with HasCoreParameters {
trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend {
val module: CanHaveScratchpadModule
val cacheBlockBytes = p(CacheBlockBytes)
val slaveNode = TLInputNode() // Up to two uses for this input node:
// 1) Frontend always exists, but may or may not have a scratchpad node
// 2) ScratchpadSlavePort always has a node, but only exists when the HellaCache has a scratchpad
val fg = LazyModule(new TLFragmenter(fetchWidth*coreInstBytes, p(CacheBlockBytes), earlyAck=true))
val ww = LazyModule(new TLWidthWidget(xLen/8))
val scratch = tileParams.dcache.flatMap(d => d.scratch.map(s =>
LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1)))))
val fg = LazyModule(new TLFragmenter(tileParams.core.fetchBytes, cacheBlockBytes, earlyAck=true))
val ww = LazyModule(new TLWidthWidget(xBytes))
val scratch = tileParams.dcache.flatMap { d => d.scratch.map(s =>
LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1), xBytes, tileParams.core.useAtomics)))
}
DisableMonitors { implicit p =>
frontend.slaveNode :*= fg.node
fg.node :*= ww.node
ww.node :*= slaveNode
scratch foreach { lm => lm.node := TLFragmenter(xLen/8, p(CacheBlockBytes), earlyAck=true)(slaveNode) }
scratch foreach { lm => lm.node := TLFragmenter(xBytes, cacheBlockBytes, earlyAck=true)(slaveNode) }
}
def findScratchpadFromICache: Option[AddressSet] = scratch.map { s =>

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@ -13,7 +13,6 @@ import freechips.rocketchip.tile.{XLen, CoreModule, CoreBundle}
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
case object PAddrBits extends Field[Int]
case object PgLevels extends Field[Int]
case object ASIdBits extends Field[Int]

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@ -25,16 +25,32 @@ trait TileParams {
trait HasTileParameters {
implicit val p: Parameters
val tileParams: TileParams = p(TileKey)
def tileParams: TileParams = p(TileKey)
val usingVM = tileParams.core.useVM
val usingUser = tileParams.core.useUser || usingVM
val usingDebug = tileParams.core.useDebug
val usingRoCC = !tileParams.rocc.isEmpty
val usingBTB = tileParams.btb.isDefined && tileParams.btb.get.nEntries > 0
val usingPTW = usingVM
val usingDataScratchpad = tileParams.dcache.flatMap(_.scratch).isDefined
val hartIdLen = p(MaxHartIdBits)
def usingVM: Boolean = tileParams.core.useVM
def usingUser: Boolean = tileParams.core.useUser || usingVM
def usingDebug: Boolean = tileParams.core.useDebug
def usingRoCC: Boolean = !tileParams.rocc.isEmpty
def usingBTB: Boolean = tileParams.btb.isDefined && tileParams.btb.get.nEntries > 0
def usingPTW: Boolean = usingVM
def usingDataScratchpad: Boolean = tileParams.dcache.flatMap(_.scratch).isDefined
def xLen: Int = p(XLen)
def xBytes: Int = xLen / 8
def pgIdxBits: Int = 12
def pgLevelBits: Int = 10 - log2Ceil(xLen / 32)
def vaddrBits: Int = pgIdxBits + pgLevels * pgLevelBits
def paddrBits: Int = p(SharedMemoryTLEdge).bundle.addressBits
def vpnBits: Int = vaddrBits - pgIdxBits
def ppnBits: Int = paddrBits - pgIdxBits
def pgLevels: Int = p(PgLevels)
def asIdBits: Int = p(ASIdBits)
def vpnBitsExtended: Int = vpnBits + (vaddrBits < xLen).toInt
def vaddrBitsExtended: Int = vpnBitsExtended + pgIdxBits
def maxPAddrBits: Int = xLen match { case 32 => 34; case 64 => 56 }
def hartIdLen: Int = p(MaxHartIdBits)
def resetVectorLen: Int = paddrBits min vaddrBitsExtended
def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + tileParams.rocc.size
}
@ -71,10 +87,9 @@ trait HasTileLinkMasterPortModule {
}
/** Some other standard inputs */
trait HasExternallyDrivenTileConstants extends Bundle {
implicit val p: Parameters
val hartid = UInt(INPUT, p(MaxHartIdBits))
val resetVector = UInt(INPUT, p(ResetVectorBits))
trait HasExternallyDrivenTileConstants extends Bundle with HasTileParameters {
val hartid = UInt(INPUT, hartIdLen)
val reset_vector = UInt(INPUT, resetVectorLen)
}
/** Base class for all Tiles that use TileLink */
@ -89,4 +104,10 @@ class BaseTileBundle[+L <: BaseTile](_outer: L) extends BareTileBundle(_outer)
with HasExternallyDrivenTileConstants
class BaseTileModule[+L <: BaseTile, +B <: BaseTileBundle[L]](_outer: L, _io: () => B) extends BareTileModule(_outer, _io)
with HasTileLinkMasterPortModule
with HasTileParameters
with HasTileLinkMasterPortModule {
require(xLen == 32 || xLen == 64)
require(paddrBits <= maxPAddrBits)
require(resetVectorLen <= xLen)
require(resetVectorLen <= vaddrBitsExtended)
}

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@ -27,14 +27,15 @@ trait CoreParams {
val nLocalInterrupts: Int
val nL2TLBEntries: Int
val jumpInFrontend: Boolean
def instBytes: Int = instBits / 8
def fetchBytes: Int = fetchWidth * instBytes
}
trait HasCoreParameters extends HasTileParameters {
val coreParams: CoreParams = tileParams.core
val xLen = p(XLen)
val fLen = xLen // TODO relax this
require(xLen == 32 || xLen == 64)
val usingMulDiv = coreParams.mulDiv.nonEmpty
val usingFPU = coreParams.fpu.nonEmpty
@ -49,24 +50,11 @@ trait HasCoreParameters extends HasTileParameters {
val coreInstBytes = coreInstBits/8
val coreDataBits = xLen max fLen
val coreDataBytes = coreDataBits/8
val coreMaxAddrBits = paddrBits max vaddrBitsExtended
val coreDCacheReqTagBits = 6
val dcacheReqTagBits = coreDCacheReqTagBits + log2Ceil(dcacheArbPorts)
def pgIdxBits = 12
def pgLevelBits = 10 - log2Ceil(xLen / 32)
def vaddrBits = pgIdxBits + pgLevels * pgLevelBits
val paddrBits = p(PAddrBits)
def ppnBits = paddrBits - pgIdxBits
def vpnBits = vaddrBits - pgIdxBits
val pgLevels = p(PgLevels)
val asIdBits = p(ASIdBits)
val vpnBitsExtended = vpnBits + (vaddrBits < xLen).toInt
val vaddrBitsExtended = vpnBitsExtended + pgIdxBits
val coreMaxAddrBits = paddrBits max vaddrBitsExtended
val maxPAddrBits = xLen match { case 32 => 34; case 64 => 56 }
require(paddrBits <= maxPAddrBits)
// Print out log of committed instructions and their writeback values.
// Requires post-processing due to out-of-order writebacks.
val enableCommitLog = false

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@ -232,7 +232,7 @@ object FType {
trait HasFPUParameters {
val fLen: Int
val xLen: Int
def xLen: Int
val minXLen = 32
val nIntTypes = log2Ceil(xLen/minXLen) + 1
val floatTypes = FType.all.filter(_.ieeeWidth <= fLen)

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@ -6,7 +6,6 @@ import Chisel._
import freechips.rocketchip.config.{Parameters, Field}
import freechips.rocketchip.coreplex.CacheBlockBytes
import freechips.rocketchip.rocket.PAddrBits
import freechips.rocketchip.tilelink.ClientMetadata
import freechips.rocketchip.util._

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@ -136,14 +136,11 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne
with HasLazyRoCCModule
with CanHaveScratchpadModule {
require(outer.p(PAddrBits) == outer.masterNode.edgesIn(0).bundle.addressBits,
s"outer.p(PAddrBits) (${outer.p(PAddrBits)}) must be == outer.masterNode.addressBits (${outer.masterNode.edgesIn(0).bundle.addressBits})")
val core = Module(p(BuildCore)(outer.p))
decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector
core.io.hartid := io.hartid // Pass through the hartid
outer.frontend.module.io.cpu <> core.io.imem
outer.frontend.module.io.resetVector := io.resetVector
outer.frontend.module.io.reset_vector := io.reset_vector
outer.frontend.module.io.hartid := io.hartid
outer.dcache.module.io.hartid := io.hartid
dcachePorts += core.io.dmem // TODO outer.dcachePorts += () => module.core.io.dmem ??
@ -208,7 +205,7 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
}
// signals that do not change based on crossing type:
rocket.module.io.hartid := io.hartid
rocket.module.io.resetVector := io.resetVector
rocket.module.io.reset_vector := io.reset_vector
}
}