riscv/rocket-chip
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Merge pull request #983 from freechipsproject/kill-paddrbits

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Remove global fields PAddrBits and ResetVectorBits
This commit is contained in:
Henry Cook
2017-09-11 12:51:10 -07:00
committed by GitHub
parent 1f606d924f 9c0bfbd500
commit 063ca0ed4a
15 changed files with 67 additions and 63 deletions
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7
src/main/scala/rocket/Frontend.scala
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@ -64,13 +64,12 @@ class Frontend(val icacheParams: ICacheParams, hartid: Int)(implicit p: Paramete
DisableMonitors { implicit p => icache.slaveNode.map { _ := slaveNode } }
}
class FrontendBundle(outer: Frontend) extends CoreBundle()(outer.p) {
class FrontendBundle(outer: Frontend) extends CoreBundle()(outer.p)
with HasExternallyDrivenTileConstants {
val cpu = new FrontendIO().flip
val ptw = new TLBPTWIO()
val tl_out = outer.masterNode.bundleOut
val tl_in = outer.slaveNode.bundleIn
val resetVector = UInt(INPUT, vaddrBitsExtended)
val hartid = UInt(INPUT, hartIdLen)
}
class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
@ -90,7 +89,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
val s1_pc = Reg(UInt(width=vaddrBitsExtended))
val s1_speculative = Reg(Bool())
val s2_valid = RegInit(false.B)
val s2_pc = RegInit(alignPC(io.resetVector))
val s2_pc = RegInit(t = UInt(width = vaddrBitsExtended), alignPC(io.reset_vector))
val s2_btb_resp_valid = if (usingBTB) Reg(Bool()) else false.B
val s2_btb_resp_bits = Reg(new BTBResp)
val s2_tlb_resp = Reg(tlb.io.resp)

17
src/main/scala/rocket/ScratchpadSlavePort.scala
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@ -12,8 +12,7 @@ import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends LazyModule
with HasCoreParameters {
class ScratchpadSlavePort(address: AddressSet, coreDataBytes: Int, usingAtomics: Boolean)(implicit p: Parameters) extends LazyModule {
val device = new SimpleDevice("dtim", Seq("sifive,dtim0"))
val node = TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters(
@ -97,23 +96,25 @@ class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends L
}
/** Mix-ins for constructing tiles that have optional scratchpads */
trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend with HasCoreParameters {
trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend {
val module: CanHaveScratchpadModule
val cacheBlockBytes = p(CacheBlockBytes)
val slaveNode = TLInputNode() // Up to two uses for this input node:
// 1) Frontend always exists, but may or may not have a scratchpad node
// 2) ScratchpadSlavePort always has a node, but only exists when the HellaCache has a scratchpad
val fg = LazyModule(new TLFragmenter(fetchWidth*coreInstBytes, p(CacheBlockBytes), earlyAck=true))
val ww = LazyModule(new TLWidthWidget(xLen/8))
val scratch = tileParams.dcache.flatMap(d => d.scratch.map(s =>
LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1)))))
val fg = LazyModule(new TLFragmenter(tileParams.core.fetchBytes, cacheBlockBytes, earlyAck=true))
val ww = LazyModule(new TLWidthWidget(xBytes))
val scratch = tileParams.dcache.flatMap { d => d.scratch.map(s =>
LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1), xBytes, tileParams.core.useAtomics)))
}
DisableMonitors { implicit p =>
frontend.slaveNode :*= fg.node
fg.node :*= ww.node
ww.node :*= slaveNode
scratch foreach { lm => lm.node := TLFragmenter(xLen/8, p(CacheBlockBytes), earlyAck=true)(slaveNode) }
scratch foreach { lm => lm.node := TLFragmenter(xBytes, cacheBlockBytes, earlyAck=true)(slaveNode) }
}
def findScratchpadFromICache: Option[AddressSet] = scratch.map { s =>

1
src/main/scala/rocket/TLB.scala
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@ -13,7 +13,6 @@ import freechips.rocketchip.tile.{XLen, CoreModule, CoreBundle}
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
case object PAddrBits extends Field[Int]
case object PgLevels extends Field[Int]
case object ASIdBits extends Field[Int]