riscv/rocket-chip
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Fetch smaller parcels from the I$

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This commit is contained in:
Andrew Waterman
2017-04-18 17:55:04 -07:00
committed by Andrew Waterman
parent c72b15f2a0
commit 061a0adceb
2 changed files with 27 additions and 14 deletions
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29
src/main/scala/rocket/ICache.scala
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@ -47,7 +47,7 @@ class ICacheBundle(outer: ICache) extends CoreBundle()(outer.p) {
val s1_kill = Bool(INPUT) // delayed one cycle w.r.t. req
val s2_kill = Bool(INPUT) // delayed two cycles; prevents I$ miss emission
val resp = Decoupled(new ICacheResp)
val resp = Decoupled(UInt(width = coreInstBits * fetchWidth))
val invalidate = Bool(INPUT)
val mem = outer.node.bundleOut
}
@ -110,7 +110,8 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
}
val s1_tag_disparity = Wire(Vec(nWays, Bool()))
val s1_dout = Wire(Vec(nWays, UInt(width = code.width(rowBits))))
val wordBits = coreInstBits * fetchWidth
val s1_dout = Wire(Vec(nWays, UInt(width = code.width(wordBits))))
val s1_dout_valid = RegNext(s0_valid)
for (i <- 0 until nWays) {
@ -119,7 +120,24 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
s1_tag_hit(i) := s1_vb && ((code.decode(tag_rdata(i)).uncorrected === s1_tag) holdUnless s1_dout_valid)
}
val data_arrays = Seq.fill(nWays) { SeqMem(nSets * refillCycles, Bits(width = code.width(rowBits))) }
require(rowBits % wordBits == 0)
val data_arrays = Seq.fill(rowBits / wordBits) { SeqMem(nSets * refillCycles, Vec(nWays, UInt(width = code.width(wordBits)))) }
for ((data_array, i) <- data_arrays zipWithIndex) {
val wen = tl_out.d.valid
when (wen) {
val idx = (refill_idx << log2Ceil(refillCycles)) | refill_cnt
val data = tl_out.d.bits.data(wordBits*(i+1)-1, wordBits*i)
data_array.write(idx, Vec.fill(nWays)(code.encode(data)), (0 until nWays).map(repl_way === _))
}
def wordMatch(addr: UInt) = addr.extract(log2Ceil(rowBytes)-1, log2Ceil(wordBits/8)) === i
val s0_raddr = s0_vaddr(untagBits-1,blockOffBits-log2Ceil(refillCycles))
val dout = data_array.read(s0_raddr, !wen && (s0_valid && wordMatch(s0_vaddr))) holdUnless s1_dout_valid
when (wordMatch(io.s1_paddr)) {
s1_dout := dout
}
}
/*
for ((data_array, i) <- data_arrays zipWithIndex) {
val wen = tl_out.d.valid && repl_way === UInt(i)
when (wen) {
@ -129,12 +147,13 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
val s0_raddr = s0_vaddr(untagBits-1,blockOffBits-log2Ceil(refillCycles))
s1_dout(i) := data_array.read(s0_raddr, !wen && s0_valid) holdUnless s1_dout_valid
}
*/
// output signals
outer.latency match {
case 1 =>
require(code.width(rowBits) == rowBits) // no ECC
io.resp.bits.datablock := Mux1H(s1_tag_hit, s1_dout)
io.resp.bits := Mux1H(s1_tag_hit, s1_dout)
io.resp.valid := s1_hit
case 2 =>
val s2_valid = RegEnable(out_valid, Bool(false), !stall)
@ -148,7 +167,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
val s2_disparity = s2_tag_disparity || s2_data_disparity
when (s2_valid && s2_disparity) { invalidate := true }
io.resp.bits.datablock := code.decode(s2_way_mux).uncorrected
io.resp.bits := code.decode(s2_way_mux).uncorrected
io.resp.valid := s2_hit && !s2_disparity
}
tl_out.a.valid := state === s_request && !io.s2_kill