diff --git a/project/build.scala b/project/build.scala
index c23b1640..529f035f 100644
--- a/project/build.scala
+++ b/project/build.scala
@@ -15,7 +15,8 @@ object BuildSettings extends Build {
     parallelExecution in Global := false,
     traceLevel   := 15,
     scalacOptions ++= Seq("-deprecation","-unchecked"),
-    libraryDependencies ++= Seq("org.scala-lang" % "scala-reflect" % scalaVersion.value)
+    libraryDependencies ++= Seq("org.scala-lang" % "scala-reflect" % scalaVersion.value),
+    addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full)
   )
 
   lazy val chisel = project in file("chisel3")
diff --git a/src/main/scala/uncore/tilelink2/SRAM.scala b/src/main/scala/uncore/tilelink2/SRAM.scala
index 2e9d9d35..25d36d5a 100644
--- a/src/main/scala/uncore/tilelink2/SRAM.scala
+++ b/src/main/scala/uncore/tilelink2/SRAM.scala
@@ -3,6 +3,7 @@
 package uncore.tilelink2
 
 import Chisel._
+import chisel3.experimental.chiselName
 import config._
 import diplomacy._
 import util._
@@ -27,7 +28,8 @@ class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)
   // We require the address range to include an entire beat (for the write mask)
   require ((address.mask & (beatBytes-1)) == beatBytes-1)
 
-  lazy val module = new LazyModuleImp(this) {
+  lazy val module = new Implementation
+  @chiselName class Implementation extends LazyModuleImp(this) {
     val io = new Bundle {
       val in = node.bundleIn
     }