riscv/rocket-chip
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Merge branch 'master' into pipeline-mmio

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Henry Cook 2017-05-03 01:59:59 -07:00 committed by GitHub
commit 05ca88fb47
1 changed files with 4 additions and 3 deletions
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src/main/scala/tile/Interrupts.scala
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@ -50,11 +50,12 @@ trait HasExternalInterruptsModule {
val periph_ips = Seq(
core.msip,
core.mtip,
core.meip,
core.seip.getOrElse(Wire(Bool())))
core.meip)
val seip = if (core.seip.isDefined) Seq(core.seip.get) else Nil
val core_ips = core.lip
(async_ips ++ periph_ips ++ core_ips).zip(io.interrupts(0)).foreach { case(c, i) => c := i }
(async_ips ++ periph_ips ++ seip ++ core_ips).zip(io.interrupts(0)).foreach { case(c, i) => c := i }
}
}