riscv/rocket-chip
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[rocket] Implement RVC

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This commit is contained in:
Andrew Waterman
2016-07-29 16:36:07 -07:00
parent c465120610
commit 058396aefe
10 changed files with 434 additions and 89 deletions
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9
src/main/scala/Configs.scala
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@ -186,7 +186,7 @@ class BaseConfig extends Config (
case RoccNPTWPorts => site(BuildRoCC).map(_.nPTWPorts).foldLeft(0)(_ + _)
case RoccNCSRs => site(BuildRoCC).map(_.csrs.size).foldLeft(0)(_ + _)
//Rocket Core Constants
case FetchWidth => 1
case FetchWidth => if (site(UseCompressed)) 2 else 1
case RetireWidth => 1
case UseVM => true
case UseUser => true
@ -216,6 +216,11 @@ class BaseConfig extends Config (
TestGeneration.addSuites(env.map(if (site(XLen) == 64) rv64ua else rv32ua))
true
}
case UseCompressed => {
val env = if(site(UseVM)) List("p","v") else List("p")
TestGeneration.addSuites(env.map(if (site(XLen) == 64) rv64uc else rv32uc))
true
}
case NExtInterrupts => 2
case AsyncMMIOChannels => false
case ExtMMIOPorts => AddrMap()
@ -234,7 +239,7 @@ class BaseConfig extends Config (
case FDivSqrt => true
case SFMALatency => 2
case DFMALatency => 3
case CoreInstBits => 32
case CoreInstBits => if (site(UseCompressed)) 16 else 32
case CoreDataBits => site(XLen)
case NCustomMRWCSRs => 0
case ResetVector => BigInt(0x1000)

10
src/main/scala/Testing.scala
View File

@ -99,6 +99,9 @@ object DefaultTestSuites {
"slt", "slti", "sra", "srai", "srl", "srli", "sub", "xor", "xori")
val rv32ui = new AssemblyTestSuite("rv32ui", rv32uiNames)(_)
val rv32ucNames = LinkedHashSet("rvc")
val rv32uc = new AssemblyTestSuite("rv32uc", rv32ucNames)(_)
val rv32umNames = LinkedHashSet("mul", "mulh", "mulhsu", "mulhu", "div", "divu", "rem", "remu")
val rv32um = new AssemblyTestSuite("rv32um", rv32umNames)(_)
@ -124,6 +127,9 @@ object DefaultTestSuites {
val rv64uaNames = rv32uaNames.map(_.replaceAll("_w","_d"))
val rv64ua = new AssemblyTestSuite("rv64ua", rv32uaNames ++ rv64uaNames)(_)
val rv64ucNames = rv32ucNames
val rv64uc = new AssemblyTestSuite("rv64uc", rv64ucNames)(_)
val rv64ufNames = LinkedHashSet("ldst", "move", "fsgnj", "fcmp", "fcvt", "fcvt_w", "fclass", "fadd", "fdiv", "fmin", "fmadd")
val rv64uf = new AssemblyTestSuite("rv64uf", rv64ufNames)(_)
val rv64ufNoDiv = new AssemblyTestSuite("rv64uf", rv64ufNames - "fdiv")(_)
@ -148,10 +154,10 @@ object DefaultTestSuites {
val rv64i = List(rv64ui, rv64si, rv64mi)
val rv64pi = List(rv64ui, rv64mi)
val benchmarks = new BenchmarkTestSuite("basic", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet(
val benchmarks = new BenchmarkTestSuite("rvi", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet(
"median", "multiply", "qsort", "towers", "vvadd", "dhrystone", "mt-matmul"))
val rv32udBenchmarks = new BenchmarkTestSuite("basic", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet(
val rv32udBenchmarks = new BenchmarkTestSuite("rvd", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet(
"mm", "spmv", "mt-vvadd"))
val emptyBmarks = new BenchmarkTestSuite("empty",