[rocket] Implement RVC
This commit is contained in:
Andrew Waterman
@ -19,6 +19,7 @@ case object UseVM extends Field[Boolean]
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case object UseUser extends Field[Boolean]
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case object UseDebug extends Field[Boolean]
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case object UseAtomics extends Field[Boolean]
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case object UseCompressed extends Field[Boolean]
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case object UsePerfCounters extends Field[Boolean]
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case object FastLoadWord extends Field[Boolean]
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case object FastLoadByte extends Field[Boolean]
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@ -42,6 +43,7 @@ trait HasCoreParameters extends HasAddrMapParameters {
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val usingDebug = p(UseDebug)
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val usingFPU = p(UseFPU)
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val usingAtomics = p(UseAtomics)
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val usingCompressed = p(UseCompressed)
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val usingFDivSqrt = p(FDivSqrt)
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val usingRoCC = !p(BuildRoCC).isEmpty
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val mulUnroll = p(MulUnroll)
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@ -65,6 +67,10 @@ trait HasCoreParameters extends HasAddrMapParameters {
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val nRoccCsrs = p(RoccNCSRs)
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val nCores = p(NTiles)
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// fetchWidth doubled, but coreInstBytes halved, for RVC
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require(fetchWidth == retireWidth * (4 / coreInstBytes))
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require(retireWidth == 1)
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// Print out log of committed instructions and their writeback values.
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// Requires post-processing due to out-of-order writebacks.
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val enableCommitLog = false
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@ -75,7 +81,7 @@ trait HasCoreParameters extends HasAddrMapParameters {
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case 64 => 50
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}
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require(paddrBits < maxPAddrBits)
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require(paddrBits <= maxPAddrBits)
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require(!fastLoadByte || fastLoadWord)
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}
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@ -153,8 +159,9 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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val ex_reg_xcpt_interrupt = Reg(Bool())
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val ex_reg_valid = Reg(Bool())
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val ex_reg_rvc = Reg(Bool())
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val ex_reg_btb_hit = Reg(Bool())
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val ex_reg_btb_resp = Reg(io.imem.btb_resp.bits)
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val ex_reg_btb_resp = Reg(new BTBResp)
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val ex_reg_xcpt = Reg(Bool())
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val ex_reg_flush_pipe = Reg(Bool())
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val ex_reg_load_use = Reg(Bool())
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@ -165,8 +172,9 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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val mem_reg_xcpt_interrupt = Reg(Bool())
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val mem_reg_valid = Reg(Bool())
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val mem_reg_rvc = Reg(Bool())
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val mem_reg_btb_hit = Reg(Bool())
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val mem_reg_btb_resp = Reg(io.imem.btb_resp.bits)
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val mem_reg_btb_resp = Reg(new BTBResp)
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val mem_reg_xcpt = Reg(Bool())
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val mem_reg_replay = Reg(Bool())
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val mem_reg_flush_pipe = Reg(Bool())
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@ -182,7 +190,6 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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val wb_reg_valid = Reg(Bool())
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val wb_reg_xcpt = Reg(Bool())
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val wb_reg_mem_xcpt = Reg(Bool())
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val wb_reg_replay = Reg(Bool())
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val wb_reg_cause = Reg(UInt())
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val wb_reg_pc = Reg(UInt())
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@ -195,13 +202,17 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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val take_pc = take_pc_mem_wb
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// decode stage
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val id_pc = io.imem.resp.bits.pc
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val id_inst = io.imem.resp.bits.data(0).toBits; require(fetchWidth == 1)
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val id_ctrl = Wire(new IntCtrlSigs()).decode(id_inst, decode_table)
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val id_raddr3 = id_inst(31,27)
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val id_raddr2 = id_inst(24,20)
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val id_raddr1 = id_inst(19,15)
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val id_waddr = id_inst(11,7)
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val ibuf = Module(new IBuf)
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val id_expanded_inst = ibuf.io.inst.map(_.bits.inst)
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val id_inst = id_expanded_inst.map(_.bits)
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ibuf.io.imem <> io.imem.resp
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ibuf.io.kill := take_pc
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val id_ctrl = Wire(new IntCtrlSigs()).decode(id_inst(0), decode_table)
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val id_raddr3 = id_expanded_inst(0).rs3
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val id_raddr2 = id_expanded_inst(0).rs2
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val id_raddr1 = id_expanded_inst(0).rs1
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val id_waddr = id_expanded_inst(0).rd
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val id_load_use = Wire(Bool())
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val id_reg_fence = Reg(init=Bool(false))
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val id_ren = IndexedSeq(id_ctrl.rxs1, id_ctrl.rxs2)
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@ -215,7 +226,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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val id_system_insn = id_ctrl.csr === CSR.I
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val id_csr_ren = (id_ctrl.csr === CSR.S || id_ctrl.csr === CSR.C) && id_raddr1 === UInt(0)
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val id_csr = Mux(id_csr_ren, CSR.R, id_ctrl.csr)
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val id_csr_addr = id_inst(31,20)
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val id_csr_addr = id_inst(0)(31,20)
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// this is overly conservative
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val safe_csrs = CSRs.sscratch :: CSRs.sepc :: CSRs.mscratch :: CSRs.mepc :: CSRs.mcause :: CSRs.mbadaddr :: Nil
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val legal_csrs = collection.mutable.LinkedHashSet(CSRs.all:_*)
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@ -225,8 +236,8 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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id_ctrl.fp && !csr.io.status.fs.orR ||
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id_ctrl.rocc && !csr.io.status.xs.orR
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// stall decode for fences (now, for AMO.aq; later, for AMO.rl and FENCE)
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val id_amo_aq = id_inst(26)
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val id_amo_rl = id_inst(25)
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val id_amo_aq = id_inst(0)(26)
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val id_amo_rl = id_inst(0)(25)
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val id_fence_next = id_ctrl.fence || id_ctrl.amo && id_amo_rl
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val id_mem_busy = !io.dmem.ordered || io.dmem.req.valid
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val id_rocc_busy = Bool(usingRoCC) &&
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@ -239,14 +250,15 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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val bpu = Module(new BreakpointUnit)
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bpu.io.status := csr.io.status
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bpu.io.bp := csr.io.bp
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bpu.io.pc := id_pc
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bpu.io.pc := ibuf.io.pc
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bpu.io.ea := mem_reg_wdata
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val id_xcpt_if = ibuf.io.inst(0).bits.pf0 || ibuf.io.inst(0).bits.pf1
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val (id_xcpt, id_cause) = checkExceptions(List(
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(csr.io.interrupt, csr.io.interrupt_cause),
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(bpu.io.xcpt_if, UInt(Causes.breakpoint)),
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(io.imem.resp.bits.xcpt_if, UInt(Causes.fault_fetch)),
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(id_illegal_insn, UInt(Causes.illegal_instruction))))
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(csr.io.interrupt, csr.io.interrupt_cause),
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(bpu.io.xcpt_if, UInt(Causes.breakpoint)),
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(id_xcpt_if, UInt(Causes.fault_fetch)),
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(id_illegal_insn, UInt(Causes.illegal_instruction))))
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val dcache_bypass_data =
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if (fastLoadByte) io.dmem.resp.bits.data
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@ -278,7 +290,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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val ex_op2 = MuxLookup(ex_ctrl.sel_alu2, SInt(0), Seq(
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A2_RS2 -> ex_rs(1).toSInt,
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A2_IMM -> ex_imm,
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A2_FOUR -> SInt(4)))
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A2_SIZE -> Mux(ex_reg_rvc, SInt(2), SInt(4))))
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val alu = Module(new ALU)
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alu.io.dw := ex_ctrl.alu_dw
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@ -299,16 +311,26 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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div.io.req.bits.tag := ex_waddr
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ex_reg_valid := !ctrl_killd
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ex_reg_replay := !take_pc && io.imem.resp.valid && io.imem.resp.bits.replay
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ex_reg_replay := !take_pc && ibuf.io.inst(0).valid && ibuf.io.inst(0).bits.replay
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ex_reg_xcpt := !ctrl_killd && id_xcpt
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ex_reg_xcpt_interrupt := !take_pc && io.imem.resp.valid && csr.io.interrupt
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ex_reg_xcpt_interrupt := !take_pc && ibuf.io.inst(0).valid && csr.io.interrupt
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when (id_xcpt) { ex_reg_cause := id_cause }
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ex_reg_btb_hit := ibuf.io.inst(0).bits.btb_hit
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when (ibuf.io.inst(0).bits.btb_hit) { ex_reg_btb_resp := ibuf.io.btb_resp }
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when (!ctrl_killd) {
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ex_ctrl := id_ctrl
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ex_reg_rvc := ibuf.io.inst(0).bits.rvc
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ex_ctrl.csr := id_csr
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ex_reg_btb_hit := io.imem.btb_resp.valid
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when (io.imem.btb_resp.valid) { ex_reg_btb_resp := io.imem.btb_resp.bits }
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when (id_xcpt) { // pass PC down ALU writeback pipeline for badaddr
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ex_ctrl.alu_fn := ALU.FN_ADD
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ex_ctrl.sel_alu1 := A1_PC
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ex_ctrl.sel_alu2 := A2_ZERO
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when (!bpu.io.xcpt_if && !ibuf.io.inst(0).bits.pf0 && ibuf.io.inst(0).bits.pf1) { // PC+2
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ex_ctrl.sel_alu2 := A2_SIZE
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ex_reg_rvc := true
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}
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}
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ex_reg_flush_pipe := id_ctrl.fence_i || id_csr_flush || csr.io.singleStep
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ex_reg_load_use := id_load_use
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@ -328,9 +350,9 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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}
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}
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}
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when (!ctrl_killd || csr.io.interrupt || io.imem.resp.bits.replay) {
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ex_reg_inst := id_inst
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ex_reg_pc := id_pc
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when (!ctrl_killd || csr.io.interrupt || ibuf.io.inst(0).bits.replay) {
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ex_reg_inst := id_inst(0)
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ex_reg_pc := ibuf.io.pc
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}
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// replay inst in ex stage?
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@ -352,18 +374,18 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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val mem_br_taken = mem_reg_wdata(0)
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val mem_br_target = mem_reg_pc.toSInt +
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Mux(mem_ctrl.branch && mem_br_taken, ImmGen(IMM_SB, mem_reg_inst),
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Mux(mem_ctrl.jal, ImmGen(IMM_UJ, mem_reg_inst), SInt(4)))
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val mem_int_wdata = Mux(mem_ctrl.jalr, mem_br_target, mem_reg_wdata.toSInt).toUInt
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Mux(mem_ctrl.jal, ImmGen(IMM_UJ, mem_reg_inst),
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Mux(mem_reg_rvc, SInt(2), SInt(4))))
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val mem_npc = (Mux(mem_ctrl.jalr, encodeVirtualAddress(mem_reg_wdata, mem_reg_wdata).toSInt, mem_br_target) & SInt(-2)).toUInt
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val mem_wrong_npc = Mux(ex_pc_valid, mem_npc =/= ex_reg_pc, Mux(io.imem.resp.valid, mem_npc =/= id_pc, Bool(true)))
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val mem_npc_misaligned = mem_npc(1)
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val mem_wrong_npc = Mux(ex_pc_valid, mem_npc =/= ex_reg_pc, Mux(ibuf.io.inst(0).valid, mem_npc =/= ibuf.io.pc, Bool(true)))
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val mem_npc_misaligned = if (usingCompressed) Bool(false) else mem_npc(1)
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val mem_int_wdata = Mux(!mem_reg_xcpt && (mem_ctrl.jalr ^ mem_npc_misaligned), mem_br_target, mem_reg_wdata.toSInt).toUInt
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val mem_cfi = mem_ctrl.branch || mem_ctrl.jalr || mem_ctrl.jal
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val mem_cfi_taken = (mem_ctrl.branch && mem_br_taken) || mem_ctrl.jalr || mem_ctrl.jal
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val mem_misprediction =
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if (p(BtbKey).nEntries == 0) mem_cfi_taken
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else mem_wrong_npc
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val want_take_pc_mem = mem_reg_valid && (mem_misprediction || mem_reg_flush_pipe)
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take_pc_mem := want_take_pc_mem && !mem_npc_misaligned
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take_pc_mem := mem_reg_valid && (mem_misprediction || mem_reg_flush_pipe)
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mem_reg_valid := !ctrl_killx
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mem_reg_replay := !take_pc_mem_wb && replay_ex
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@ -373,6 +395,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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when (ex_pc_valid) {
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mem_ctrl := ex_ctrl
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mem_reg_rvc := ex_reg_rvc
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mem_reg_load := ex_ctrl.mem && isRead(ex_ctrl.mem_cmd)
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mem_reg_store := ex_ctrl.mem && isWrite(ex_ctrl.mem_cmd)
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mem_reg_btb_hit := ex_reg_btb_hit
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@ -389,13 +412,13 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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}
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val (mem_new_xcpt, mem_new_cause) = checkExceptions(List(
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(mem_reg_load && bpu.io.xcpt_ld, UInt(Causes.breakpoint)),
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(mem_reg_store && bpu.io.xcpt_st, UInt(Causes.breakpoint)),
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(want_take_pc_mem && mem_npc_misaligned, UInt(Causes.misaligned_fetch)),
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(mem_ctrl.mem && io.dmem.xcpt.ma.st, UInt(Causes.misaligned_store)),
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(mem_ctrl.mem && io.dmem.xcpt.ma.ld, UInt(Causes.misaligned_load)),
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(mem_ctrl.mem && io.dmem.xcpt.pf.st, UInt(Causes.fault_store)),
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(mem_ctrl.mem && io.dmem.xcpt.pf.ld, UInt(Causes.fault_load))))
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(mem_reg_load && bpu.io.xcpt_ld, UInt(Causes.breakpoint)),
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(mem_reg_store && bpu.io.xcpt_st, UInt(Causes.breakpoint)),
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(mem_npc_misaligned, UInt(Causes.misaligned_fetch)),
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(mem_ctrl.mem && io.dmem.xcpt.ma.st, UInt(Causes.misaligned_store)),
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(mem_ctrl.mem && io.dmem.xcpt.ma.ld, UInt(Causes.misaligned_load)),
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(mem_ctrl.mem && io.dmem.xcpt.pf.st, UInt(Causes.fault_store)),
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(mem_ctrl.mem && io.dmem.xcpt.pf.ld, UInt(Causes.fault_load))))
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val (mem_xcpt, mem_cause) = checkExceptions(List(
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(mem_reg_xcpt_interrupt || mem_reg_xcpt, mem_reg_cause),
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@ -412,11 +435,10 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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wb_reg_valid := !ctrl_killm
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wb_reg_replay := replay_mem && !take_pc_wb
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wb_reg_xcpt := mem_xcpt && !take_pc_wb
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wb_reg_mem_xcpt := mem_reg_valid && mem_new_xcpt && !(mem_reg_xcpt_interrupt || mem_reg_xcpt)
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when (mem_xcpt) { wb_reg_cause := mem_cause }
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when (mem_reg_valid || mem_reg_replay || mem_reg_xcpt_interrupt) {
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wb_ctrl := mem_ctrl
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wb_reg_wdata := Mux(mem_ctrl.fp && mem_ctrl.wxd, io.fpu.toint_data, mem_int_wdata)
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wb_reg_wdata := Mux(!mem_reg_xcpt && mem_ctrl.fp && mem_ctrl.wxd, io.fpu.toint_data, mem_int_wdata)
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when (mem_ctrl.rocc) {
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wb_reg_rs2 := mem_reg_rs2
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}
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@ -434,7 +456,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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// writeback arbitration
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val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).toBool
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val dmem_resp_fpu = io.dmem.resp.bits.tag(0).toBool
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val dmem_resp_waddr = io.dmem.resp.bits.tag >> 1
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val dmem_resp_waddr = io.dmem.resp.bits.tag(5, 1)
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val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data
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val dmem_resp_replay = dmem_resp_valid && io.dmem.resp.bits.replay
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@ -479,7 +501,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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io.rocc.csr <> csr.io.rocc.csr
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csr.io.rocc.interrupt <> io.rocc.interrupt
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csr.io.pc := wb_reg_pc
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csr.io.badaddr := Mux(wb_reg_mem_xcpt, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), wb_reg_pc)
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csr.io.badaddr := encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata)
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io.ptw.ptbr := csr.io.ptbr
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io.ptw.invalidate := csr.io.fatc
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io.ptw.status := csr.io.status
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@ -495,7 +517,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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(io.fpu.dec.ren3, id_raddr3),
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(io.fpu.dec.wen, id_waddr))
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val sboard = new Scoreboard(32)
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val sboard = new Scoreboard(32, true)
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sboard.clear(ll_wen, ll_waddr)
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val id_sboard_hazard = checkHazards(hazard_targets, sboard.read _)
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sboard.set(wb_set_sboard && wb_wen, wb_waddr)
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@ -542,7 +564,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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id_ctrl.rocc && rocc_blocked || // reduce activity while RoCC is busy
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id_do_fence ||
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csr.io.csr_stall
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ctrl_killd := !io.imem.resp.valid || io.imem.resp.bits.replay || take_pc || ctrl_stalld || csr.io.interrupt
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ctrl_killd := !ibuf.io.inst(0).valid || ibuf.io.inst(0).bits.replay || take_pc || ctrl_stalld || csr.io.interrupt
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io.imem.req.valid := take_pc
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io.imem.req.bits.speculative := !take_pc_wb
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@ -552,33 +574,35 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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mem_npc)).toUInt // mispredicted branch
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io.imem.flush_icache := wb_reg_valid && wb_ctrl.fence_i && !io.dmem.s2_nack
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io.imem.flush_tlb := csr.io.fatc
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io.imem.resp.ready := !ctrl_stalld || csr.io.interrupt || take_pc_mem
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io.imem.btb_update.valid := mem_reg_valid && !mem_npc_misaligned && mem_wrong_npc && mem_cfi_taken && !take_pc_wb
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ibuf.io.inst(0).ready := !ctrl_stalld || csr.io.interrupt
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io.imem.btb_update.valid := (mem_reg_replay && mem_reg_btb_hit) || (mem_reg_valid && !take_pc_wb && mem_wrong_npc)
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io.imem.btb_update.bits.isValid := !mem_reg_replay && mem_cfi
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io.imem.btb_update.bits.isJump := mem_ctrl.jal || mem_ctrl.jalr
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io.imem.btb_update.bits.isReturn := mem_ctrl.jalr && mem_reg_inst(19,15) === BitPat("b00??1")
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io.imem.btb_update.bits.pc := mem_reg_pc
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io.imem.btb_update.bits.target := io.imem.req.bits.pc
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io.imem.btb_update.bits.br_pc := mem_reg_pc
|
||||
io.imem.btb_update.bits.br_pc := (if (usingCompressed) mem_reg_pc + Mux(mem_reg_rvc, UInt(0), UInt(2)) else mem_reg_pc)
|
||||
io.imem.btb_update.bits.pc := ~(~io.imem.btb_update.bits.br_pc | (coreInstBytes*fetchWidth-1))
|
||||
io.imem.btb_update.bits.prediction.valid := mem_reg_btb_hit
|
||||
io.imem.btb_update.bits.prediction.bits := mem_reg_btb_resp
|
||||
|
||||
io.imem.bht_update.valid := mem_reg_valid && mem_ctrl.branch && !take_pc_wb
|
||||
io.imem.bht_update.bits.pc := mem_reg_pc
|
||||
io.imem.bht_update.valid := mem_reg_valid && !take_pc_wb && mem_ctrl.branch
|
||||
io.imem.bht_update.bits.pc := io.imem.btb_update.bits.pc
|
||||
io.imem.bht_update.bits.taken := mem_br_taken
|
||||
io.imem.bht_update.bits.mispredict := mem_wrong_npc
|
||||
io.imem.bht_update.bits.prediction := io.imem.btb_update.bits.prediction
|
||||
|
||||
io.imem.ras_update.valid := mem_reg_valid && io.imem.btb_update.bits.isJump && !mem_npc_misaligned && !take_pc_wb
|
||||
io.imem.ras_update.valid := mem_reg_valid && !take_pc_wb
|
||||
io.imem.ras_update.bits.returnAddr := mem_int_wdata
|
||||
io.imem.ras_update.bits.isCall := mem_ctrl.wxd && mem_waddr(0)
|
||||
io.imem.ras_update.bits.isCall := io.imem.btb_update.bits.isJump && mem_waddr(0)
|
||||
io.imem.ras_update.bits.isReturn := io.imem.btb_update.bits.isReturn
|
||||
io.imem.ras_update.bits.prediction := io.imem.btb_update.bits.prediction
|
||||
|
||||
io.fpu.valid := !ctrl_killd && id_ctrl.fp
|
||||
io.fpu.killx := ctrl_killx
|
||||
io.fpu.killm := killm_common
|
||||
io.fpu.inst := id_inst
|
||||
io.fpu.inst := id_inst(0)
|
||||
io.fpu.fromint_data := ex_rs(0)
|
||||
io.fpu.dmem_resp_val := dmem_resp_valid && dmem_resp_fpu
|
||||
io.fpu.dmem_resp_data := io.dmem.resp.bits.data_word_bypass
|
||||
@ -659,21 +683,22 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
|
||||
Cat(msb, ea(vaddrBits-1,0))
|
||||
}
|
||||
|
||||
class Scoreboard(n: Int)
|
||||
class Scoreboard(n: Int, zero: Boolean = false)
|
||||
{
|
||||
def set(en: Bool, addr: UInt): Unit = update(en, _next | mask(en, addr))
|
||||
def clear(en: Bool, addr: UInt): Unit = update(en, _next & ~mask(en, addr))
|
||||
def read(addr: UInt): Bool = r(addr)
|
||||
def readBypassed(addr: UInt): Bool = _next(addr)
|
||||
|
||||
private val r = Reg(init=Bits(0, n))
|
||||
private val _r = Reg(init=Bits(0, n))
|
||||
private val r = if (zero) (_r >> 1 << 1) else _r
|
||||
private var _next = r
|
||||
private var ens = Bool(false)
|
||||
private def mask(en: Bool, addr: UInt) = Mux(en, UInt(1) << addr, UInt(0))
|
||||
private def update(en: Bool, update: UInt) = {
|
||||
_next = update
|
||||
ens = ens || en
|
||||
when (ens) { r := _next }
|
||||
when (ens) { _r := _next }
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user