riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

minor Changes needed to support formal tests

Browse Source
This commit is contained in:
Jacob Chang
2016-12-01 14:55:25 -08:00
parent 4234cff074
commit 053f81d7c6
5 changed files with 28 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/uncore/tilelink2/Fragmenter.scala
View File

@ -13,7 +13,7 @@ import scala.math.{min,max}
// Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint
// Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin)
// Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides
class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) extends LazyModule
class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false) extends LazyModule
{
require (isPow2 (maxSize))
require (isPow2 (minSize))