riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

minor Changes needed to support formal tests

Browse Source
This commit is contained in:
Jacob Chang
2016-12-01 14:55:25 -08:00
parent 4234cff074
commit 053f81d7c6
5 changed files with 28 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
src/main/scala/uncore/tilelink2/Edges.scala
View File

@ -95,6 +95,24 @@ class TLEdge(
staticHasData(x).map(Bool(_)).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size