riscv/rocket-chip
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Merge branch 'master' into tl-error

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This commit is contained in:
Henry Cook 2017-09-27 14:50:17 -07:00 committed by GitHub
commit 05112b49a3
14 changed files with 93 additions and 53 deletions
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4
project/plugins.sbt
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@ -4,8 +4,10 @@ addSbtPlugin("com.typesafe.sbt" % "sbt-ghpages" % "0.5.3")
addSbtPlugin("com.typesafe.sbt" % "sbt-site" % "0.8.1")
addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.6.1")
addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.7.0")
addSbtPlugin("org.xerial.sbt" % "sbt-pack" % "0.8.0")
addSbtPlugin("com.eed3si9n" % "sbt-unidoc" % "0.3.3")
addSbtPlugin("org.scoverage" % "sbt-scoverage" % "1.5.1")

8
src/main/scala/coreplex/Configs.scala
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@ -151,10 +151,12 @@ class WithBufferlessBroadcastHub extends Config((site, here, up) => {
* DO NOT use this configuration.
*/
class WithStatelessBridge extends Config((site, here, up) => {
case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = { case (q, _) =>
implicit val p = q
case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = { coreplex =>
implicit val p = coreplex.p
val cork = LazyModule(new TLCacheCork(unsafe = true))
(cork.node, cork.node)
val ww = LazyModule(new TLWidthWidget(coreplex.sbusBeatBytes))
ww.node :*= cork.node
(cork.node, ww.node, () => None)
})
})

24
src/main/scala/coreplex/MemoryBus.scala
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@ -22,12 +22,13 @@ case object BroadcastKey extends Field(BroadcastParams())
case class BankedL2Params(
nMemoryChannels: Int = 1,
nBanksPerChannel: Int = 1,
coherenceManager: (Parameters, HasMemoryBus) => (TLInwardNode, TLOutwardNode) = { case (q, _) =>
implicit val p = q
val MemoryBusParams(_, blockBytes, _, _) = p(MemoryBusKey)
coherenceManager: HasMemoryBus => (TLInwardNode, TLOutwardNode, () => Option[Bool]) = { coreplex =>
implicit val p = coreplex.p
val BroadcastParams(nTrackers, bufferless) = p(BroadcastKey)
val bh = LazyModule(new TLBroadcast(blockBytes, nTrackers, bufferless))
(bh.node, bh.node)
val bh = LazyModule(new TLBroadcast(coreplex.memBusBlockBytes, nTrackers, bufferless))
val ww = LazyModule(new TLWidthWidget(coreplex.sbusBeatBytes))
ww.node :*= bh.node
(bh.node, ww.node, () => None)
}) {
val nBanks = nMemoryChannels*nBanksPerChannel
}
@ -53,24 +54,25 @@ class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWr
trait HasMemoryBus extends HasSystemBus with HasPeripheryBus with HasInterruptBus {
private val mbusParams = p(MemoryBusKey)
private val MemoryBusParams(beatBytes, blockBytes, _, _) = mbusParams
private val l2Params = p(BankedL2Key)
val MemoryBusParams(memBusBeatBytes, memBusBlockBytes, _, _) = mbusParams
val BankedL2Params(nMemoryChannels, nBanksPerChannel, coherenceManager) = l2Params
val nBanks = l2Params.nBanks
val cacheBlockBytes = blockBytes
val cacheBlockBytes = memBusBlockBytes
private val (in, out, halt) = coherenceManager(this)
def memBusCanCauseHalt: () => Option[Bool] = halt
require (isPow2(nMemoryChannels) || nMemoryChannels == 0)
require (isPow2(nBanksPerChannel))
require (isPow2(blockBytes))
require (isPow2(memBusBlockBytes))
private val (in, out) = coherenceManager(p, this)
private val mask = ~BigInt((nBanks-1) * blockBytes)
private val mask = ~BigInt((nBanks-1) * memBusBlockBytes)
val memBuses = Seq.tabulate(nMemoryChannels) { channel =>
val mbus = new MemoryBus(mbusParams)
for (bank <- 0 until nBanksPerChannel) {
val offset = (bank * nMemoryChannels) + channel
ForceFanout(a = true) { implicit p => in := sbus.toMemoryBus }
mbus.fromCoherenceManager := TLFilter(TLFilter.Mmask(AddressSet(offset * blockBytes, mask)))(out)
mbus.fromCoherenceManager := TLFilter(TLFilter.Mmask(AddressSet(offset * memBusBlockBytes, mask)))(out)
}
mbus
}

6
src/main/scala/coreplex/RocketCoreplex.scala
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@ -84,7 +84,11 @@ trait HasRocketTiles extends HasSystemBus
lip.foreach { coreIntXbar.intnode := _ } // lip
wrapper.coreIntNode := coreIntXbar.intnode
wrapper.intOutputNode.foreach { plic.intnode := _ }
wrapper.intOutputNode.foreach { case int =>
val rocketIntXing = LazyModule(new IntXing(wrapper.outputInterruptXingLatency))
rocketIntXing.intnode := int
plic.intnode := rocketIntXing.intnode
}
wrapper
}

12
src/main/scala/rocket/CSR.scala
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@ -151,11 +151,12 @@ class PerfCounterIO(implicit p: Parameters) extends CoreBundle
class TracedInstruction(implicit p: Parameters) extends CoreBundle {
val valid = Bool()
val addr = UInt(width = coreMaxAddrBits)
val iaddr = UInt(width = coreMaxAddrBits)
val insn = UInt(width = iLen)
val priv = UInt(width = 3)
val exception = Bool()
val cause = UInt(width = 1 + log2Ceil(xLen))
val interrupt = Bool()
val cause = UInt(width = log2Ceil(xLen))
val tval = UInt(width = coreMaxAddrBits max iLen)
}
@ -519,7 +520,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
assert(!reg_singleStepped || io.retire === UInt(0))
val epc = ~(~io.pc | (coreInstBytes-1))
val write_badaddr = cause isOneOf (Causes.illegal_instruction, Causes.breakpoint,
val write_badaddr = exception && cause.isOneOf(Causes.illegal_instruction, Causes.breakpoint,
Causes.misaligned_load, Causes.misaligned_store,
Causes.load_access, Causes.store_access, Causes.fetch_access,
Causes.load_page_fault, Causes.store_page_fault, Causes.fetch_page_fault)
@ -771,9 +772,10 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
t.exception := io.retire >= i && exception
t.valid := io.retire > i || t.exception
t.insn := insn
t.addr := io.pc
t.iaddr := io.pc
t.priv := Cat(reg_debug, reg_mstatus.prv)
t.cause := Cat(cause(xLen-1), cause(log2Ceil(xLen)-1, 0))
t.cause := cause
t.interrupt := cause(xLen-1)
t.tval := badaddr_value
}

15
src/main/scala/rocket/DCache.scala
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@ -11,7 +11,8 @@ import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import TLMessages._
class DCacheErrors(implicit p: Parameters) extends L1HellaCacheBundle()(p) {
class DCacheErrors(implicit p: Parameters) extends L1HellaCacheBundle()(p)
with CanHaveErrors {
val correctable = (cacheParams.tagECC.canCorrect || cacheParams.dataECC.canCorrect).option(Valid(UInt(width = paddrBits)))
val uncorrectable = (cacheParams.tagECC.canDetect || cacheParams.dataECC.canDetect).option(Valid(UInt(width = paddrBits)))
val bus = Valid(UInt(width = paddrBits))
@ -41,9 +42,9 @@ class DCacheDataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val wMask = if (nWays == 1) eccMask else (0 until nWays).flatMap(i => eccMask.map(_ && io.req.bits.way_en(i)))
val wWords = io.req.bits.wdata.grouped(encBits * (wordBits / eccBits))
val addr = io.req.bits.addr >> rowOffBits
val dcache_data_arrays = Seq.fill(rowBytes / wordBytes) { SeqMem(nSets * refillCycles, Vec(nWays * (wordBits / eccBits), UInt(width = encBits))) }
val rdata = for ((array, i) <- dcache_data_arrays zipWithIndex) yield {
val valid = io.req.valid && (Bool(dcache_data_arrays.size == 1) || io.req.bits.wordMask(i))
val data_arrays = Seq.fill(rowBytes / wordBytes) { SeqMem(nSets * refillCycles, Vec(nWays * (wordBits / eccBits), UInt(width = encBits))) }
val rdata = for ((array, i) <- data_arrays zipWithIndex) yield {
val valid = io.req.valid && (Bool(data_arrays.size == 1) || io.req.bits.wordMask(i))
when (valid && io.req.bits.write) {
val wData = wWords(i).grouped(encBits)
array.write(addr, Vec((0 until nWays).flatMap(i => wData)), wMask)
@ -78,7 +79,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
// tags
val replacer = cacheParams.replacement
val metaArb = Module(new Arbiter(new DCacheMetadataReq, 8))
val dcache_tag_array = SeqMem(nSets, Vec(nWays, UInt(width = tECC.width(metaArb.io.out.bits.data.getWidth))))
val tag_array = SeqMem(nSets, Vec(nWays, UInt(width = tECC.width(metaArb.io.out.bits.data.getWidth))))
// data
val data = Module(new DCacheDataArray)
@ -188,9 +189,9 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
when (metaReq.valid && metaReq.bits.write) {
val wdata = tECC.encode(metaReq.bits.data.asUInt)
val wmask = if (nWays == 1) Seq(true.B) else metaReq.bits.way_en.toBools
dcache_tag_array.write(metaIdx, Vec.fill(nWays)(wdata), wmask)
tag_array.write(metaIdx, Vec.fill(nWays)(wdata), wmask)
}
val s1_meta = dcache_tag_array.read(metaIdx, metaReq.valid && !metaReq.bits.write)
val s1_meta = tag_array.read(metaIdx, metaReq.valid && !metaReq.bits.write)
val s1_meta_uncorrected = s1_meta.map(tECC.decode(_).uncorrected.asTypeOf(new L1Metadata))
val s1_tag = s1_paddr >> untagBits
val s1_meta_hit_way = s1_meta_uncorrected.map(r => r.coh.isValid() && r.tag === s1_tag).asUInt

14
src/main/scala/rocket/ICache.scala
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@ -36,7 +36,9 @@ class ICacheReq(implicit p: Parameters) extends CoreBundle()(p) with HasL1ICache
val addr = UInt(width = vaddrBits)
}
class ICacheErrors(implicit p: Parameters) extends CoreBundle()(p) with HasL1ICacheParameters {
class ICacheErrors(implicit p: Parameters) extends CoreBundle()(p)
with HasL1ICacheParameters
with CanHaveErrors {
val correctable = (cacheParams.tagECC.canDetect || cacheParams.dataECC.canDetect).option(Valid(UInt(width = paddrBits)))
val uncorrectable = (cacheParams.itimAddr.nonEmpty && cacheParams.dataECC.canDetect).option(Valid(UInt(width = paddrBits)))
}
@ -174,12 +176,12 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
v
}
val icache_tag_array = SeqMem(nSets, Vec(nWays, UInt(width = tECC.width(1 + tagBits))))
val tag_rdata = icache_tag_array.read(s0_vaddr(untagBits-1,blockOffBits), !refill_done && s0_valid)
val tag_array = SeqMem(nSets, Vec(nWays, UInt(width = tECC.width(1 + tagBits))))
val tag_rdata = tag_array.read(s0_vaddr(untagBits-1,blockOffBits), !refill_done && s0_valid)
val accruedRefillError = Reg(Bool())
when (refill_done) {
val enc_tag = tECC.encode(Cat(tl_out.d.bits.error, refill_tag))
icache_tag_array.write(refill_idx, Vec.fill(nWays)(enc_tag), Seq.tabulate(nWays)(repl_way === _))
tag_array.write(refill_idx, Vec.fill(nWays)(enc_tag), Seq.tabulate(nWays)(repl_way === _))
}
val vb_array = Reg(init=Bits(0, nSets*nWays))
@ -220,8 +222,8 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
assert(!(s1_valid || s1_slaveValid) || PopCount(s1_tag_hit zip s1_tag_disparity map { case (h, d) => h && !d }) <= 1)
require(tl_out.d.bits.data.getWidth % wordBits == 0)
val icache_data_arrays = Seq.fill(tl_out.d.bits.data.getWidth / wordBits) { SeqMem(nSets * refillCycles, Vec(nWays, UInt(width = dECC.width(wordBits)))) }
for ((data_array, i) <- icache_data_arrays zipWithIndex) {
val data_arrays = Seq.fill(tl_out.d.bits.data.getWidth / wordBits) { SeqMem(nSets * refillCycles, Vec(nWays, UInt(width = dECC.width(wordBits)))) }
for ((data_array, i) <- data_arrays zipWithIndex) {
def wordMatch(addr: UInt) = addr.extract(log2Ceil(tl_out.d.bits.data.getWidth/8)-1, log2Ceil(wordBits/8)) === i
def row(addr: UInt) = addr(untagBits-1, blockOffBits-log2Ceil(refillCycles))
val s0_ren = (s0_valid && wordMatch(s0_vaddr)) || (s0_slaveValid && wordMatch(s0_slaveAddr))

12
src/main/scala/rocket/NBDcache.scala
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@ -628,12 +628,12 @@ class DataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val resp = Wire(Vec(rowWords, Bits(width = encRowBits)))
val r_raddr = RegEnable(io.read.bits.addr, io.read.valid)
for (i <- 0 until resp.size) {
val nbdcache_data_array = SeqMem(nSets*refillCycles, Vec(rowWords, Bits(width=encDataBits)))
val array = SeqMem(nSets*refillCycles, Vec(rowWords, Bits(width=encDataBits)))
when (wway_en.orR && io.write.valid && io.write.bits.wmask(i)) {
val data = Vec.fill(rowWords)(io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i))
nbdcache_data_array.write(waddr, data, wway_en.toBools)
array.write(waddr, data, wway_en.toBools)
}
resp(i) := nbdcache_data_array.read(raddr, rway_en.orR && io.read.valid).asUInt
resp(i) := array.read(raddr, rway_en.orR && io.read.valid).asUInt
}
for (dw <- 0 until rowWords) {
val r = Vec(resp.map(_(encDataBits*(dw+1)-1,encDataBits*dw)))
@ -645,12 +645,12 @@ class DataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
}
} else {
for (w <- 0 until nWays) {
val nbdcache_data_array = SeqMem(nSets*refillCycles, Vec(rowWords, Bits(width=encDataBits)))
val array = SeqMem(nSets*refillCycles, Vec(rowWords, Bits(width=encDataBits)))
when (io.write.bits.way_en(w) && io.write.valid) {
val data = Vec.tabulate(rowWords)(i => io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i))
nbdcache_data_array.write(waddr, data, io.write.bits.wmask.toBools)
array.write(waddr, data, io.write.bits.wmask.toBools)
}
io.resp(w) := nbdcache_data_array.read(raddr, io.read.bits.way_en(w) && io.read.valid).asUInt
io.resp(w) := array.read(raddr, io.read.bits.way_en(w) && io.read.valid).asUInt
}
}

10
src/main/scala/rocket/RocketCore.scala
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@ -675,16 +675,16 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
when (t.valid) {
when (wfd) {
printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.addr, t.insn, rd, rd+UInt(32))
printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd+UInt(32))
}
.elsewhen (wxd && rd =/= UInt(0) && has_data) {
printf ("%d 0x%x (0x%x) x%d 0x%x\n", t.priv, t.addr, t.insn, rd, rf_wdata)
printf ("%d 0x%x (0x%x) x%d 0x%x\n", t.priv, t.iaddr, t.insn, rd, rf_wdata)
}
.elsewhen (wxd && rd =/= UInt(0) && !has_data) {
printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.addr, t.insn, rd, rd)
printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd)
}
.otherwise {
printf ("%d 0x%x (0x%x)\n", t.priv, t.addr, t.insn)
printf ("%d 0x%x (0x%x)\n", t.priv, t.iaddr, t.insn)
}
}
@ -694,7 +694,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
}
else {
printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
io.hartid, csr.io.time(31,0), csr.io.trace(0).valid, csr.io.trace(0).addr(vaddrBitsExtended-1, 0),
io.hartid, csr.io.time(31,0), csr.io.trace(0).valid, csr.io.trace(0).iaddr(vaddrBitsExtended-1, 0),
Mux(rf_wen && !(wb_set_sboard && wb_wen), rf_waddr, UInt(0)), rf_wdata, rf_wen,
wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs(0))),
wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs(1))),

26
src/main/scala/tile/RocketTile.scala
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@ -20,6 +20,7 @@ case class RocketTileParams(
dataScratchpadBytes: Int = 0,
boundaryBuffers: Boolean = false,
trace: Boolean = false,
hcfOnUncorrectable: Boolean = false,
name: Option[String] = Some("tile"),
externalMasterBuffers: Int = 0,
externalSlaveBuffers: Int = 0) extends TileParams {
@ -131,6 +132,9 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p
class RocketTileBundle(outer: RocketTile) extends BaseTileBundle(outer)
with HasExternalInterruptsBundle
with CanHaveScratchpadBundle
with CanHaltAndCatchFire {
val halt_and_catch_fire = outer.rocketParams.hcfOnUncorrectable.option(Bool(OUTPUT))
}
class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => new RocketTileBundle(outer))
with HasExternalInterruptsModule
@ -138,9 +142,12 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne
with CanHaveScratchpadModule {
val core = Module(p(BuildCore)(outer.p))
val uncorrectable = RegInit(Bool(false))
decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector
core.io.hartid := io.hartid // Pass through the hartid
io.trace.foreach { _ := core.io.trace }
io.halt_and_catch_fire.foreach { _ := uncorrectable }
outer.frontend.module.io.cpu <> core.io.imem
outer.frontend.module.io.reset_vector := io.reset_vector
outer.frontend.module.io.hartid := io.hartid
@ -154,6 +161,12 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne
core.io.rocc.busy := roccCore.busy
core.io.rocc.interrupt := roccCore.interrupt
when(!uncorrectable) { uncorrectable :=
List(outer.frontend.module.io.errors, outer.dcache.module.io.errors)
.flatMap { e => e.uncorrectable.map(_.valid) }
.reduceOption(_||_)
.getOrElse(false.B)
}
// TODO eliminate this redundancy
val h = dcachePorts.size
@ -200,25 +213,26 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
def outputInterruptXingLatency: Int
rocket.intOutputNode.foreach { rocketIntOutputNode =>
val outXing = LazyModule(new IntXing(outputInterruptXingLatency))
intOutputNode.get := outXing.intnode
outXing.intnode := rocketIntOutputNode
}
intOutputNode.foreach { _ := rocket.intOutputNode.get }
lazy val module = new LazyModuleImp(this) {
val io = new CoreBundle with HasExternallyDrivenTileConstants with CanHaveInstructionTracePort {
val io = new CoreBundle
with HasExternallyDrivenTileConstants
with CanHaveInstructionTracePort
with CanHaltAndCatchFire {
val master = masterNode.bundleOut
val slave = slaveNode.bundleIn
val outputInterrupts = intOutputNode.map(_.bundleOut)
val asyncInterrupts = asyncIntNode.bundleIn
val periphInterrupts = periphIntNode.bundleIn
val coreInterrupts = coreIntNode.bundleIn
val halt_and_catch_fire = rocket.module.io.halt_and_catch_fire.map(_.cloneType)
}
// signals that do not change based on crossing type:
rocket.module.io.hartid := io.hartid
rocket.module.io.reset_vector := io.reset_vector
io.trace.foreach { _ := rocket.module.io.trace.get }
io.halt_and_catch_fire.foreach { _ := rocket.module.io.halt_and_catch_fire.get }
}
}

5
src/main/scala/util/ECC.scala
View File

@ -173,3 +173,8 @@ class SECDEDTest extends Module
io.correctable := d.correctable
io.uncorrectable := d.uncorrectable
}
trait CanHaveErrors extends Bundle {
val correctable: Option[ValidIO[UInt]]
val uncorrectable: Option[ValidIO[UInt]]
}

4
src/main/scala/util/Misc.scala
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@ -26,6 +26,10 @@ trait Clocked extends Bundle {
val reset = Bool()
}
trait CanHaltAndCatchFire extends Bundle {
val halt_and_catch_fire: Option[Bool]
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}

2
vsrc/AsyncResetReg.v
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@ -54,7 +54,9 @@ module AsyncResetReg (
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND = {1{$random}};
if (~rst) begin
q = _RAND[0];
end
`endif
end
`endif // `ifdef RANDOMIZE

2
vsrc/plusarg_reader.v
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@ -2,7 +2,7 @@
// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),
// but Incisive demands them. These default values should never be used.
module plusarg_reader #(FORMAT="borked=%d", DEFAULT=0) (
module plusarg_reader #(parameter FORMAT="borked=%d", DEFAULT=0) (
output [31:0] out
);