From 04d92dddbd6ab471c35ea02bce976fdbe7490c8d Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Mon, 2 Nov 2015 17:01:28 -0800 Subject: [PATCH] add back decoupled NASTI connection at edge of RocketChip --- src/main/scala/RocketChip.scala | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 884cffad..36c966d7 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -110,12 +110,14 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters { uncore.io.tiles_cached <> tileList.map(_.io.cached).flatten uncore.io.tiles_uncached <> tileList.map(_.io.uncached).flatten io.host <> uncore.io.host - io.mem <> uncore.io.mem if (p(UseBackupMemoryPort)) { io.mem_backup_ctrl <> uncore.io.mem_backup_ctrl } - // Memory cache type should be normal non-cacheable bufferable - io.mem.map(_.ar.bits.cache := UInt("b0011")) - io.mem.map(_.aw.bits.cache := UInt("b0011")) + io.mem.zip(uncore.io.mem).foreach { case (outer, inner) => + TopUtils.connectNasti(outer, inner) + // Memory cache type should be normal non-cacheable bufferable + outer.ar.bits.cache := UInt("b0011") + outer.aw.bits.cache := UInt("b0011") + } // tie off the mmio port val errslave = Module(new NastiErrorSlave)