riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

MergedPutRegression: wait for all Puts if tlMaxClientXacts != 3

Browse Source
This commit is contained in:
Wesley W. Terpstra 2016-11-18 16:15:02 -08:00
parent cd19bf65b8
commit 04b9a68ea6
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/groundtest/Regression.scala
View File

@ -599,7 +599,7 @@ class MergedPutRegression(implicit p: Parameters) extends Regression()(p)
val delaying = Reg(init = Bool(false)) val delaying = Reg(init = Bool(false))
val (put_cnt, put_done) = Counter(io.mem.acquire.fire(), tlMaxClientXacts) val (put_cnt, put_done) = Counter(io.mem.acquire.fire(), tlMaxClientXacts)
val (delay_cnt, delay_done) = Counter(delaying, 8) val (delay_cnt, delay_done) = Counter(delaying, 8)
val put_acked = Reg(UInt(width = 3), init = UInt(0)) val put_acked = Reg(UInt(width = tlMaxClientXacts), init = UInt(0))
io.mem.acquire.valid := sending && !delaying io.mem.acquire.valid := sending && !delaying
io.mem.acquire.bits := Mux(state === s_put, io.mem.acquire.bits := Mux(state === s_put,