riscv/rocket-chip
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Emit plusArgs for unit tests

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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
This commit is contained in:
Schuyler Eldridge 2018-01-15 17:54:40 -05:00
parent 09c1d034fa
commit 04af785a5f
1 changed files with 2 additions and 1 deletions
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src/main/scala/unittest/UnitTest.scala
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@ -5,7 +5,7 @@ package freechips.rocketchip.unittest
import Chisel._ import Chisel._
import chisel3.experimental.MultiIOModule import chisel3.experimental.MultiIOModule
import freechips.rocketchip.config._ import freechips.rocketchip.config._
import freechips.rocketchip.util.SimpleTimer import freechips.rocketchip.util._
trait UnitTestIO { trait UnitTestIO {
val finished = Bool(OUTPUT) val finished = Bool(OUTPUT)
@ -22,6 +22,7 @@ trait UnitTestLegacyModule extends HasUnitTestIO {
trait UnitTestModule extends MultiIOModule with HasUnitTestIO { trait UnitTestModule extends MultiIOModule with HasUnitTestIO {
val io = IO(new Bundle with UnitTestIO) val io = IO(new Bundle with UnitTestIO)
ElaborationArtefacts.add("plusArgs", PlusArgArtefacts.serialize_cHeader)
} }
abstract class UnitTest(val timeout: Int = 4096) extends Module with UnitTestLegacyModule { abstract class UnitTest(val timeout: Int = 4096) extends Module with UnitTestLegacyModule {