From 04593d433e58b1d8bfdbe157e51b041c04bd2807 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sun, 25 May 2014 23:59:24 -0700 Subject: [PATCH] clean up Int <-> Boolean conversion stuff --- rocket/src/main/scala/ecc.scala | 8 ++++---- rocket/src/main/scala/tile.scala | 4 ++-- rocket/src/main/scala/util.scala | 14 ++++++++++---- 3 files changed, 16 insertions(+), 10 deletions(-) diff --git a/rocket/src/main/scala/ecc.scala b/rocket/src/main/scala/ecc.scala index 01164e88..cc116ae5 100644 --- a/rocket/src/main/scala/ecc.scala +++ b/rocket/src/main/scala/ecc.scala @@ -47,8 +47,8 @@ class ParityCode extends Code class SECCode extends Code { def width(k: Int) = { - val m = log2Up(k) + 1 - !isPow2(k) - k + m + ((1 << m) < m+k+1) + val m = k.log2 + 1 + k + m + ((1 << m) < m+k+1).toInt } def encode(x: Bits) = { val k = x.getWidth @@ -57,7 +57,7 @@ class SECCode extends Code val y = for (i <- 1 to n) yield { if (isPow2(i)) { - val r = for (j <- 1 to n; if j != i && (j & i).toBoolean) + val r = for (j <- 1 to n; if j != i && (j & i) != 0) yield x(mapping(j)) r reduce (_^_) } else @@ -71,7 +71,7 @@ class SECCode extends Code val p2 = for (i <- 0 until log2Up(n)) yield 1 << i val syndrome = p2 map { i => - val r = for (j <- 1 to n; if (j & i).toBoolean) + val r = for (j <- 1 to n; if (j & i) != 0) yield y(j-1) r reduce (_^_) } diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index 94beb86d..93c2c068 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -23,11 +23,11 @@ case class RocketConfiguration(tl: TileLinkConfiguration, as: AddressSpaceConfig class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module(_reset = resetSignal) { - val memPorts = 2 + !confIn.rocc.isEmpty // Number of ports to outer memory system from tile: 1 from I$, 1 from D$, maybe 1 from Rocc + val memPorts = 2 + (!confIn.rocc.isEmpty).toInt // Number of ports to outer memory system from tile: 1 from I$, 1 from D$, maybe 1 from Rocc val dcachePortId = 0 val icachePortId = 1 val roccPortId = 2 - val dcachePorts = 2 + !confIn.rocc.isEmpty // Number of ports into D$: 1 from core, 1 from PTW, maybe 1 from RoCC + val dcachePorts = 2 + (!confIn.rocc.isEmpty).toInt // Number of ports into D$: 1 from core, 1 from PTW, maybe 1 from RoCC implicit val tlConf = confIn.tl implicit val lnConf = confIn.tl.ln implicit val icConf = confIn.icache diff --git a/rocket/src/main/scala/util.scala b/rocket/src/main/scala/util.scala index 6de69590..e08791ef 100644 --- a/rocket/src/main/scala/util.scala +++ b/rocket/src/main/scala/util.scala @@ -4,8 +4,12 @@ import Chisel._ import uncore._ import scala.math._ -class BooleanToInt(x: Int) { - def toBoolean: Boolean = if (x != 0) true else false +class Unsigned(x: Int) { + require(x >= 0) + def size: Int = { require(x > 0); ceil(log(x)/log(2)).toInt } + def log2: Int = { require(x > 0); floor(log(x)/log(2)).toInt } + def isPow2: Boolean = x > 0 && (x & (x-1)) == 0 + def nextPow2: Int = if (x == 0) 1 else 1 << size } object Util { @@ -15,8 +19,10 @@ object Util { implicit def seqToVec[T <: Data](x: Iterable[T]): Vec[T] = Vec(x) implicit def wcToUInt(c: WideCounter): UInt = c.value - implicit def booleanToInt(x: Boolean): Int = if (x) 1 else 0 - implicit def intToBooleanToInt(x: Int): BooleanToInt = new BooleanToInt(x) + implicit def intToUnsigned(x: Int): Unsigned = new Unsigned(x) + implicit def booleanToIntConv(x: Boolean) = new AnyRef { + def toInt: Int = if (x) 1 else 0 + } } import Util._