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Improve logical ops in AMOALU

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As with integer ALU, shave off some muxing.
This commit is contained in:
Andrew Waterman 2017-04-30 02:22:19 -07:00
parent f49172b5bc
commit 044b6ed3f9
1 changed files with 21 additions and 10 deletions
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31
src/main/scala/uncore/util/AmoAlu.scala
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@ -70,9 +70,11 @@ class AMOALU(operandBits: Int, rhsIsAligned: Boolean = false)(implicit p: Parame
else new StoreGen(io.typ, io.addr, io.rhs, operandBits/8) else new StoreGen(io.typ, io.addr, io.rhs, operandBits/8)
val rhs = storegen.wordData val rhs = storegen.wordData
val sgned = io.cmd === M_XA_MIN || io.cmd === M_XA_MAX
val max = io.cmd === M_XA_MAX || io.cmd === M_XA_MAXU val max = io.cmd === M_XA_MAX || io.cmd === M_XA_MAXU
val min = io.cmd === M_XA_MIN || io.cmd === M_XA_MINU val min = io.cmd === M_XA_MIN || io.cmd === M_XA_MINU
val add = io.cmd === M_XA_ADD
val logic_and = io.cmd === M_XA_OR || io.cmd === M_XA_AND
val logic_xor = io.cmd === M_XA_XOR || io.cmd === M_XA_OR
val adder_out = val adder_out =
if (operandBits == 32) io.lhs + rhs if (operandBits == 32) io.lhs + rhs
@ -81,9 +83,15 @@ class AMOALU(operandBits: Int, rhsIsAligned: Boolean = false)(implicit p: Parame
(io.lhs & mask) + (rhs & mask) (io.lhs & mask) + (rhs & mask)
} }
val less = val less = {
if (operandBits == 32) Mux(io.lhs(31) === rhs(31), io.lhs < rhs, Mux(sgned, io.lhs(31), io.rhs(31))) val sgned = {
else { val mask = M_XA_MIN ^ M_XA_MINU
(io.cmd & mask) === (M_XA_MIN & mask)
}
if (operandBits == 32) {
Mux(io.lhs(31) === rhs(31), io.lhs < rhs, Mux(sgned, io.lhs(31), io.rhs(31)))
} else {
val word = !io.typ(0) val word = !io.typ(0)
val cmp_lhs = Mux(word && !io.addr(2), io.lhs(31), io.lhs(63)) val cmp_lhs = Mux(word && !io.addr(2), io.lhs(31), io.lhs(63))
val cmp_rhs = Mux(word && !io.addr(2), rhs(31), rhs(63)) val cmp_rhs = Mux(word && !io.addr(2), rhs(31), rhs(63))
@ -93,13 +101,16 @@ class AMOALU(operandBits: Int, rhsIsAligned: Boolean = false)(implicit p: Parame
val lt = Mux(word, Mux(io.addr(2), lt_hi, lt_lo), lt_hi || eq_hi && lt_lo) val lt = Mux(word, Mux(io.addr(2), lt_hi, lt_lo), lt_hi || eq_hi && lt_lo)
Mux(cmp_lhs === cmp_rhs, lt, Mux(sgned, cmp_lhs, cmp_rhs)) Mux(cmp_lhs === cmp_rhs, lt, Mux(sgned, cmp_lhs, cmp_rhs))
} }
}
val out = Mux(io.cmd === M_XA_ADD, adder_out, val minmax = Mux(Mux(less, min, max), io.lhs, storegen.data)
Mux(io.cmd === M_XA_AND, io.lhs & rhs, val logic =
Mux(io.cmd === M_XA_OR, io.lhs | rhs, Mux(logic_and, io.lhs & rhs, 0.U) |
Mux(io.cmd === M_XA_XOR, io.lhs ^ rhs, Mux(logic_xor, io.lhs ^ rhs, 0.U)
Mux(Mux(less, min, max), io.lhs, val out =
storegen.data))))) Mux(add, adder_out,
Mux(logic_and || logic_xor, logic,
minmax))
val wmask = FillInterleaved(8, storegen.mask) val wmask = FillInterleaved(8, storegen.mask)
io.out := wmask & out | ~wmask & io.lhs io.out := wmask & out | ~wmask & io.lhs