riscv/rocket-chip
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tilelink: add Bus.toSyncSlaves for easy BufferChain attachment

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Wesley W. Terpstra committed 2017-09-07 16:03:35 -07:00
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commit 040f7e1d49
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src/main/scala/tilelink/Bus.scala
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@@ -79,7 +79,7 @@ abstract class TLBusWrapper(params: TLBusParams, val busName: String)(implicit p
def bufferToSlaves: TLOutwardNode = outwardBufNode def bufferToSlaves: TLOutwardNode = outwardBufNode
def toAsyncSlaves(sync: Int = 3, name: Option[String] = None): TLAsyncOutwardNode = { def toAsyncSlaves(sync: Int = 3, name: Option[String] = None, addBuffers: Int = 0): TLAsyncOutwardNode = {
val source = LazyModule(new TLAsyncCrossingSource(sync)) val source = LazyModule(new TLAsyncCrossingSource(sync))
name.foreach{ n => source.suggestName(s"${busName}_${n}_TLAsyncCrossingSource")} name.foreach{ n => source.suggestName(s"${busName}_${n}_TLAsyncCrossingSource")}
source.node :*= outwardNode source.node :*= outwardNode