Added temporary ioMemHub and made coherence hub implementations depend on it rather than ioMem
This commit is contained in:
Henry Cook
parent
3f998b1353
commit
040aa9fe02
@ -3,13 +3,39 @@ package rocket
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import Chisel._
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import Constants._
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class MemData extends Bundle {
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val data = Bits(width = MEM_DATA_BITS)
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}
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class MemReqCmd() extends Bundle
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{
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val rw = Bool()
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val addr = UFix(PADDR_BITS - OFFSET_BITS)
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val tag = Bits(MEM_TAG_BITS)
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}
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class MemResp () extends Bundle
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{
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val tag = Bits(MEM_TAG_BITS)
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val data = Bits(width = MEM_DATA_BITS)
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val valid = Bool()
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}
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class ioMemHub() extends Bundle
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{
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val req_cmd = (new ioDecoupled) { new MemReqCmd() }.flip
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val req_data = (new ioDecoupled) { new MemData() }.flip
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val resp = new MemResp()
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}
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class HubMemReq extends Bundle {
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val rw = Bool()
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val addr = UFix(width = PADDR_BITS-OFFSET_BITS)
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val tag = Bits(width = GLOBAL_XACT_ID_BITS)
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// Figure out which data-in port to pull from
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val data_idx = Bits(width = TILE_ID_BITS)
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val is_probe_rep = Bool()
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val req_cmd = (new ioDecoupled) { new MemReqCmd() }
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val req_data = (new ioDecoupled) { new MemData() }
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}
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class HubProbeRep extends Bundle {
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val reply = (new ioDecoupled) { new ProbeReply }
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val data_idx = Bits(width = log2up(NTILES))
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}
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class TrackerAllocReq extends Bundle {
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@ -18,9 +44,6 @@ class TrackerAllocReq extends Bundle {
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val data_valid = Bool()
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}
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class MemData extends Bundle {
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val data = Bits(width = MEM_DATA_BITS)
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}
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class TransactionInit extends Bundle {
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val t_type = Bits(width = TTYPE_BITS)
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@ -49,15 +72,13 @@ class ProbeReply extends Bundle {
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class ProbeReplyData extends MemData
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class TransactionReply extends Bundle {
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class TransactionReply extends MemData {
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val t_type = Bits(width = TTYPE_BITS)
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val has_data = Bool()
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val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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}
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class TransactionReplyData extends MemData
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class TransactionFinish extends Bundle {
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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}
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@ -70,7 +91,6 @@ class ioTileLink extends Bundle {
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val probe_rep = (new ioDecoupled) { new ProbeReply() }.flip
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val probe_rep_data = (new ioDecoupled) { new ProbeReplyData() }.flip
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val xact_rep = (new ioDecoupled) { new TransactionReply() }
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val xact_rep_data = (new ioDecoupled) { new TransactionReplyData() }
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val xact_finish = (new ioDecoupled) { new TransactionFinish() }.flip
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}
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@ -160,18 +180,21 @@ trait FourStateCoherence extends CoherencePolicy {
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class XactTracker(id: Int) extends Component with CoherencePolicy {
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val io = new Bundle {
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val alloc_req = (new ioDecoupled) { new TrackerAllocReq() }
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val probe_rep = (new ioDecoupled) { new HubProbeRep() }
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val can_alloc = Bool(INPUT)
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val xact_finish = Bool(INPUT)
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val p_rep_has_data = Bool(INPUT)
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val p_rep_data_idx = Bits(log2up(NTILES), INPUT)
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val p_rep_cnt_dec = Bits(NTILES, INPUT)
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val p_req_cnt_inc = Bits(NTILES, INPUT)
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val p_rep_data = (new ioDecoupled) { new ProbeReplyData() }
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val x_init_data = (new ioDecoupled) { new TransactionInitData() }
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val mem_req = (new ioDecoupled) { new HubMemReq() }.flip
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val probe_req = (new ioDecoupled) { new ProbeRequest() }.flip
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val busy = Bool(OUTPUT)
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val addr = Bits(PADDR_BITS, OUTPUT)
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val init_tile_id = Bits(TILE_ID_BITS, OUTPUT)
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val p_rep_tile_id = Bits(log2up(NTILES), INPUT)
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val tile_xact_id = Bits(TILE_XACT_ID_BITS, OUTPUT)
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val sharer_count = Bits(TILE_ID_BITS, OUTPUT)
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val t_type = Bits(TTYPE_BITS, OUTPUT)
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@ -183,8 +206,14 @@ class XactTracker(id: Int) extends Component with CoherencePolicy {
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val send_x_rep_ack = Bool(OUTPUT)
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}
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def sendProbeReqType(t_type: UFix, global_state: UFix): UFix = {
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MuxCase(P_COPY, Array((t_type === X_READ_SHARED) -> P_DOWNGRADE,
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(t_type === X_READ_EXCLUSIVE) -> P_INVALIDATE,
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(t_type === X_READ_UNCACHED) -> P_COPY,
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(t_type === X_WRITE_UNCACHED) -> P_INVALIDATE))
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}
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val s_idle :: s_mem_r :: s_mem_w :: mem_wr :: s_probe :: Nil = Enum(5){ UFix() }
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val s_idle :: s_mem_r :: s_mem_w :: s_mem_wr :: s_probe :: s_busy :: Nil = Enum(6){ UFix() }
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val state = Reg(resetVal = s_idle)
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val addr_ = Reg{ Bits() }
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val t_type_ = Reg{ Bits() }
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@ -192,73 +221,99 @@ class XactTracker(id: Int) extends Component with CoherencePolicy {
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val tile_xact_id_ = Reg{ Bits() }
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val probe_done = Reg{ Bits() }
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val mem_count = Reg(resetVal = UFix(0, width = log2up(REFILL_CYCLES)))
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val p_rep_count = Reg(resetVal = UFix(0, width = log2up(NTILES)))
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val p_req_flags = Reg(resetVal = UFix(0, width = NTILES))
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val p_rep_data_idx_ = Reg{ Bits() }
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val x_init_data_needs_wb = Reg{ Bool() }
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val p_rep_data_needs_wb = Reg{ Bool() }
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io.busy := state != s_idle
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io.addr := addr_
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io.init_tile_id := init_tile_id_
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io.tile_xact_id := tile_xact_id_
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io.sharer_count := UFix(NTILES) // TODO: Broadcast only
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io.t_type := t_type_
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/*
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class HubMemReq extends Bundle {
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val rw = Bool()
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val addr = UFix(width = PADDR_BITS-OFFSET_BITS)
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val tag = Bits(width = GLOBAL_XACT_ID_BITS)
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// Figure out which data-in port to pull from
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val data_idx = Bits(width = TILE_ID_BITS)
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val is_probe_rep = Bool()
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}
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class TrackerAllocReq extends Bundle {
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val xact_init = new TransactionInit()
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val t_type = Bits(width = TTYPE_BITS)
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val has_data = Bool()
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val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
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val address = Bits(width = PADDR_BITS)
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val init_tile_id = Bits(width = TILE_ID_BITS)
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val data_valid = Bool()
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*/
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/*
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when( alloc_req.valid && can_alloc ) {
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valid := Bool(true)
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addr := alloc_req.bits.xact_init.address
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t_type := alloc_req.bits.xact_init.t_type
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init_tile_id := alloc_req.bits.init_tile_id
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tile_xact_id := alloc_req.bits.xact_init.tile_xact_id
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[counter] := REFILL_CYCLES-1 if alloc_req.bits.xact_init.has_data else 0
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}
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when ( alloc_req.bits.data_valid ) {
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io.mem_req.valid :=
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io.mem_req.bits.rw :=
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io.mem_req.bits.addr :=
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io.mem_req.bits.tag :=
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io.mem_req.bits.data_idx :=
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io.mem_req.bits.is_probe_rep :=
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:= io.mem.ready
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}
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when( p_rep_has_data ) {
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io.mem_req.valid :=
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io.mem_req.bits.rw :=
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io.mem_req.bits.addr :=
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io.mem_req.bits.tag :=
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io.mem_req.bits.data_idx :=
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io.mem_req.bits.is_probe_rep :=
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:= io.mem.ready
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io.mem_req.valid := Bool(false)
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io.mem_req.bits.req_cmd.bits.rw := state === s_mem_w || state === s_mem_wr
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io.mem_req.bits.req_cmd.bits.addr := addr_
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io.mem_req.bits.req_cmd.bits.tag := UFix(id)
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// := io.mem.ready //sent mem req
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io.probe_req.valid := Bool(false)
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io.probe_req.bits.p_type := sendProbeReqType(t_type_, UFix(0))
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io.probe_req.bits.global_xact_id := UFix(id)
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io.probe_req.bits.address := addr_
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// := io.probe_req.ready //got through arbiter ---- p_rep_dec_arr
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io.push_p_req := Bits(0, width = NTILES)
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io.pop_p_rep := Bits(0, width = NTILES)
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io.pop_p_rep_data := Bits(0, width = NTILES)
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io.pop_x_init := Bool(false)
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io.pop_x_init_data := Bool(false)
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io.send_x_rep_ack := Bool(false)
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switch (state) {
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is(s_idle) {
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when( io.alloc_req.valid && io.can_alloc ) {
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addr_ := io.alloc_req.bits.xact_init.address
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t_type_ := io.alloc_req.bits.xact_init.t_type
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init_tile_id_ := io.alloc_req.bits.init_tile_id
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tile_xact_id_ := io.alloc_req.bits.xact_init.tile_xact_id
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x_init_data_needs_wb := io.alloc_req.bits.xact_init.has_data
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p_rep_count := UFix(NTILES)
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p_req_flags := ~Bits(0, width = NTILES)
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state := s_probe
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io.pop_x_init := Bool(true)
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}
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}
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is(s_mem_r) {
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io.mem_req.valid := Bool(true)
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when(io.mem_req.ready) { state := s_busy }
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}
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is(s_mem_w) {
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io.mem_req.valid := Bool(true)
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when(io.mem_req.ready) { state := s_busy }
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}
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is(s_mem_wr) {
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when(io.probe_rep.bits.reply.bits.has_data) {
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//io.pop_p_rep(p_rep_data_idx) := io.mem_req_rdy
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//io.pop_p_rep_data(p_rep_data_idx) := io.mem_req_rdy //TODO
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} . otherwise {
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//io.pop_x_init := io.mem_req_rdy
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//io.pop_x_init_data := io.mem_req_rdy
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}
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io.mem_req.valid := Bool(true)
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when(io.mem_req.ready) { state := s_mem_r }
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}
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is(s_probe) {
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when(p_req_flags.orR) {
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io.push_p_req := p_req_flags
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io.probe_req.valid := Bool(true)
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}
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when(io.p_req_cnt_inc.orR) {
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p_req_flags := p_req_flags & ~io.p_req_cnt_inc // unflag sent reqs
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}
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val p_rep_has_data = Bool(INPUT)
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val p_rep_data_idx = Bits(log2up(NTILES), INPUT)
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val p_rep_cnt_dec = Bits(NTILES, INPUT)
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when(io.p_rep_cnt_dec.orR) {
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val p_rep_count_next = p_rep_count - PopCount(io.p_rep_cnt_dec)
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p_rep_count := p_rep_count_next
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when(p_rep_count_next === UFix(0)) {
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state := s_busy //TODO: XXXXXXXXXX
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}
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}
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when(p_rep_has_data) {
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p_rep_data_needs_wb := Bool(true)
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p_rep_data_idx_ := p_rep_data_idx
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}
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}
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is(s_busy) {
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when (io.xact_finish) {
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state := s_idle
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}
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}
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}
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val mem_req = (new ioDecoupled) { new HubMemReq() }.flip
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val probe_req = (new ioDecoupled) { new ProbeRequest() }.flip
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push_p_req = Bits(0, width = NTILES)
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pop_p_rep = Bits(0, width = NTILES)
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pop_p_rep_data = Bits(0, width = NTILES)
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pop_x_init = Bool(false)
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pop_x_init_data = Bool(false)
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send_x_rep_ack = Bool(false)
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}
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*/
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//TODO: Decrement the probe count when final data piece is written
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// Connent io.mem.ready sig to correct pop* outputs
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// P_rep and x_init must be popped on same cycle of receipt
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@ -269,35 +324,24 @@ abstract class CoherenceHub extends Component with CoherencePolicy
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class CoherenceHubNull extends Component {
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val io = new Bundle {
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val tile = new ioTileLink()
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val mem = new ioMem()
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val mem = new ioMemHub()
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}
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val x_init = io.tile.xact_init
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val is_write = x_init.bits.t_type === X_WRITE_UNCACHED
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x_init.ready := io.mem.req_rdy
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io.mem.req_val := x_init.valid
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io.mem.req_rw := is_write
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io.mem.req_tag := x_init.bits.tile_xact_id
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io.mem.req_addr := x_init.bits.address
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x_init.ready := io.mem.req_cmd.ready
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io.mem.req_cmd.valid := x_init.valid
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io.mem.req_cmd.bits.rw := is_write
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io.mem.req_cmd.bits.tag := x_init.bits.tile_xact_id
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io.mem.req_cmd.bits.addr := x_init.bits.address
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io.mem.req_data <> io.tile.xact_init_data
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val x_rep = io.tile.xact_rep
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x_rep.bits.t_type := Bits(width = TTYPE_BITS)
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x_rep.bits.has_data := !is_write
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x_rep.bits.tile_xact_id := Mux(is_write, x_init.bits.tile_xact_id, io.mem.resp_tag)
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x_rep.bits.t_type := X_READ_EXCLUSIVE
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x_rep.bits.tile_xact_id := Mux(is_write, x_init.bits.tile_xact_id, io.mem.resp.tag)
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x_rep.bits.global_xact_id := UFix(0) // don't care
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x_rep.valid := io.mem.resp_val
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//TODO:
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val x_init_data = io.tile.xact_init_data
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val x_rep_data = io.tile.xact_rep_data
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x_init_data.ready := io.mem.req_rdy
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io.mem.req_wdata := x_init_data.bits.data
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x_rep_data.bits.data := io.mem.resp_data
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x_rep_data.valid := io.mem.resp_val
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// Should be:
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//io.mem.req_data <> x_init_data
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//x_rep_data <> io.mem.resp_data
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x_rep.bits.data := io.mem.resp.data
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x_rep.valid := io.mem.resp.valid
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}
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@ -319,7 +363,7 @@ class CoherenceHubNoDir extends CoherenceHub {
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val io = new Bundle {
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val tiles = Vec(NTILES) { new ioTileLink() }
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val mem = new ioMem
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val mem = new ioMemHub
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}
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val trackerList = (0 until NGLOBAL_XACTS).map(new XactTracker(_))
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@ -333,8 +377,6 @@ class CoherenceHubNoDir extends CoherenceHub {
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val send_x_rep_ack_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
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val do_free_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
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val p_rep_has_data_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
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val p_rep_data_idx_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=log2up(NTILES))} }
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val p_rep_cnt_dec_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=NTILES)} }
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val p_req_cnt_inc_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=NTILES)} }
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@ -347,8 +389,6 @@ class CoherenceHubNoDir extends CoherenceHub {
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sh_count_arr.write( UFix(i), trackerList(i).io.sharer_count)
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send_x_rep_ack_arr.write(UFix(i), trackerList(i).io.send_x_rep_ack)
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trackerList(i).io.xact_finish := do_free_arr.read(UFix(i))
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trackerList(i).io.p_rep_has_data := p_rep_has_data_arr.read(UFix(i))
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trackerList(i).io.p_rep_data_idx := p_rep_data_idx_arr.read(UFix(i))
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trackerList(i).io.p_rep_cnt_dec := p_rep_cnt_dec_arr.read(UFix(i))
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trackerList(i).io.p_req_cnt_inc := p_req_cnt_inc_arr.read(UFix(i))
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}
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@ -362,22 +402,16 @@ class CoherenceHubNoDir extends CoherenceHub {
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// Reply to initial requestor
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// Forward memory responses from mem to tile
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val xrep_cnt = Reg(resetVal = UFix(0, log2up(REFILL_CYCLES)))
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val xrep_cnt_next = xrep_cnt + UFix(1)
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when (io.mem.resp_val) { xrep_cnt := xrep_cnt_next }
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val idx = io.mem.resp_tag
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val readys = Bits(width = NTILES)
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val idx = io.mem.resp.tag
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for( j <- 0 until NTILES ) {
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io.tiles(j).xact_rep.bits.t_type := getTransactionReplyType(t_type_arr.read(idx), sh_count_arr.read(idx))
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io.tiles(j).xact_rep.bits.tile_xact_id := tile_xact_id_arr.read(idx)
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io.tiles(j).xact_rep.bits.global_xact_id := idx
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io.tiles(j).xact_rep_data.bits.data := io.mem.resp_data
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readys := Mux(xrep_cnt === UFix(0), io.tiles(j).xact_rep.ready && io.tiles(j).xact_rep_data.ready, io.tiles(j).xact_rep_data.ready)
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io.tiles(j).xact_rep.valid := (UFix(j) === init_tile_id_arr.read(idx)) && ((io.mem.resp_val && xrep_cnt === UFix(0)) || send_x_rep_ack_arr.read(idx))
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io.tiles(j).xact_rep_data.valid := (UFix(j) === init_tile_id_arr.read(idx))
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io.tiles(j).xact_rep.bits.data := io.mem.resp.data
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io.tiles(j).xact_rep.valid := (UFix(j) === init_tile_id_arr.read(idx)) && (io.mem.resp.valid || send_x_rep_ack_arr.read(idx))
|
||||
}
|
||||
// If there were a ready signal due to e.g. intervening network use:
|
||||
//io.mem.resp_rdy := readys(init_tile_id_arr.read(idx)).xact_rep.ready
|
||||
//io.mem.resp.ready := io.tiles(init_tile_id_arr.read(idx)).xact_rep.ready
|
||||
|
||||
// Create an arbiter for the one memory port
|
||||
// We have to arbitrate between the different trackers' memory requests
|
||||
@ -387,33 +421,30 @@ class CoherenceHubNoDir extends CoherenceHub {
|
||||
for( i <- 0 until NGLOBAL_XACTS ) {
|
||||
mem_req_arb.io.in(i) <> trackerList(i).io.mem_req
|
||||
}
|
||||
mem_req_arb.io.out.ready := io.mem.req_rdy
|
||||
io.mem.req_val := mem_req_arb.io.out.valid
|
||||
io.mem.req_rw := mem_req_arb.io.out.bits.rw
|
||||
io.mem.req_tag := mem_req_arb.io.out.bits.tag
|
||||
io.mem.req_addr := mem_req_arb.io.out.bits.addr
|
||||
io.mem.req_wdata := MuxLookup(mem_req_arb.io.out.bits.data_idx,
|
||||
Bits(0, width = MEM_DATA_BITS),
|
||||
(0 until NTILES).map( j =>
|
||||
UFix(j) -> Mux(mem_req_arb.io.out.bits.is_probe_rep,
|
||||
io.tiles(j).probe_rep_data.bits.data,
|
||||
io.tiles(j).xact_init_data.bits.data)))
|
||||
//mem_req_arb.io.out.ready := io.mem.req_cmd.ready || io.mem.req_data.ready
|
||||
io.mem.req_cmd <> mem_req_arb.io.out.bits.req_cmd
|
||||
io.mem.req_data <> mem_req_arb.io.out.bits.req_data
|
||||
//io.mem.req_wdata := MuxLookup(mem_req_arb.io.out.bits.data_idx,
|
||||
// Bits(0, width = MEM_DATA_BITS),
|
||||
// (0 until NTILES).map( j =>
|
||||
// UFix(j) -> Mux(mem_req_arb.io.out.bits.is_probe_rep,
|
||||
// io.tiles(j).probe_rep_data.bits.data,
|
||||
// io.tiles(j).xact_init_data.bits.data)))
|
||||
|
||||
// Handle probe replies, which may or may not have data
|
||||
for( j <- 0 until NTILES ) {
|
||||
val p_rep = io.tiles(j).probe_rep
|
||||
val p_rep_data = io.tiles(j).probe_rep_data
|
||||
val idx = p_rep.bits.global_xact_id
|
||||
p_rep_has_data_arr.write(idx, p_rep.valid && p_rep.bits.has_data && p_rep_data.valid)
|
||||
p_rep_data_idx_arr.write(idx, UFix(j))
|
||||
p_rep.ready := foldR(trackerList.map(_.io.pop_p_rep(j)))(_ || _)
|
||||
p_rep_data.ready := foldR(trackerList.map(_.io.pop_p_rep_data(j)))(_ || _)
|
||||
}
|
||||
for( i <- 0 until NGLOBAL_XACTS ) {
|
||||
trackerList(i).io.p_rep_data := MuxLookup(trackerList(i).io.p_rep_tile_id, Bits(0), (0 until NTILES).map { j => UFix(j) -> io.tiles(j).probe_rep_data })
|
||||
val flags = Bits(width = NTILES)
|
||||
for( j <- 0 until NTILES) {
|
||||
val p_rep = io.tiles(j).probe_rep
|
||||
flags(j) := p_rep.valid && !p_rep.bits.has_data && (p_rep.bits.global_xact_id === UFix(i))
|
||||
flags(j) := p_rep.valid && (p_rep.bits.global_xact_id === UFix(i))
|
||||
}
|
||||
p_rep_cnt_dec_arr.write(UFix(i), flags)
|
||||
}
|
||||
@ -448,6 +479,8 @@ class CoherenceHubNoDir extends CoherenceHub {
|
||||
trackerList(i).io.can_alloc := alloc_arb.io.in(i).ready
|
||||
trackerList(i).io.alloc_req.bits := init_arb.io.out.bits
|
||||
trackerList(i).io.alloc_req.valid := init_arb.io.out.valid
|
||||
|
||||
trackerList(i).io.x_init_data := MuxLookup(trackerList(i).io.init_tile_id, Bits(0), (0 until NTILES).map { j => UFix(j) -> io.tiles(j).xact_init_data })
|
||||
}
|
||||
|
||||
for( j <- 0 until NTILES ) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user