riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Take mprv calculation off critical path

Browse Source
This commit is contained in:
Andrew Waterman 2017-03-15 15:21:13 -07:00
parent f0796f0509
commit 03fb334c4c
2 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/rocket/CSR.scala
View File

@ -18,6 +18,7 @@ class MStatus extends Bundle {
val debug = Bool() val debug = Bool()
val isa = UInt(width = 32) val isa = UInt(width = 32)
val dprv = UInt(width = PRV.SZ) // effective privilege for data accesses
val prv = UInt(width = PRV.SZ) // not truly part of mstatus, but convenient val prv = UInt(width = PRV.SZ) // not truly part of mstatus, but convenient
val sd = Bool() val sd = Bool()
val zero2 = UInt(width = 27) val zero2 = UInt(width = 27)
@ -463,6 +464,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
io.status.isa := reg_misa io.status.isa := reg_misa
io.status.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0) io.status.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0)
io.status.sxl := (if (usingVM) log2Ceil(xLen) - 4 else 0) io.status.sxl := (if (usingVM) log2Ceil(xLen) - 4 else 0)
io.status.dprv := Reg(next = Mux(reg_mstatus.mprv, reg_mstatus.mpp, reg_mstatus.prv))
if (xLen == 32) if (xLen == 32)
io.status.sd_rv32 := io.status.sd io.status.sd_rv32 := io.status.sd

3
src/main/scala/rocket/TLB.scala
View File

@ -63,8 +63,7 @@ class TLB(lgMaxSize: Int, entries: Int)(implicit edge: TLEdgeOut, p: Parameters)
val r_refill_waddr = Reg(UInt(width = log2Ceil(normalEntries))) val r_refill_waddr = Reg(UInt(width = log2Ceil(normalEntries)))
val r_req = Reg(new TLBReq(lgMaxSize)) val r_req = Reg(new TLBReq(lgMaxSize))
val do_mprv = io.ptw.status.mprv && !io.req.bits.instruction val priv = Mux(io.req.bits.instruction, io.ptw.status.prv, io.ptw.status.dprv)
val priv = Mux(do_mprv, io.ptw.status.mpp, io.ptw.status.prv)
val priv_s = priv(0) val priv_s = priv(0)
val priv_uses_vm = priv <= PRV.S val priv_uses_vm = priv <= PRV.S
val vm_enabled = Bool(usingVM) && io.ptw.ptbr.mode(io.ptw.ptbr.mode.getWidth-1) && priv_uses_vm && !io.req.bits.passthrough val vm_enabled = Bool(usingVM) && io.ptw.ptbr.mode(io.ptw.ptbr.mode.getWidth-1) && priv_uses_vm && !io.req.bits.passthrough