riscv/rocket-chip
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Take mprv calculation off critical path

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This commit is contained in:
Andrew Waterman
2017-03-15 15:21:13 -07:00
parent f0796f0509
commit 03fb334c4c
2 changed files with 3 additions and 2 deletions
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src/main/scala/rocket/TLB.scala
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@ -63,8 +63,7 @@ class TLB(lgMaxSize: Int, entries: Int)(implicit edge: TLEdgeOut, p: Parameters)
val r_refill_waddr = Reg(UInt(width = log2Ceil(normalEntries)))
val r_req = Reg(new TLBReq(lgMaxSize))
val do_mprv = io.ptw.status.mprv && !io.req.bits.instruction
val priv = Mux(do_mprv, io.ptw.status.mpp, io.ptw.status.prv)
val priv = Mux(io.req.bits.instruction, io.ptw.status.prv, io.ptw.status.dprv)
val priv_s = priv(0)
val priv_uses_vm = priv <= PRV.S
val vm_enabled = Bool(usingVM) && io.ptw.ptbr.mode(io.ptw.ptbr.mode.getWidth-1) && priv_uses_vm && !io.req.bits.passthrough