riscv/rocket-chip
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Take mprv calculation off critical path

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This commit is contained in:
Andrew Waterman
2017-03-15 15:21:13 -07:00
parent f0796f0509
commit 03fb334c4c
2 changed files with 3 additions and 2 deletions
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2
src/main/scala/rocket/CSR.scala
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@ -18,6 +18,7 @@ class MStatus extends Bundle {
val debug = Bool()
val isa = UInt(width = 32)
val dprv = UInt(width = PRV.SZ) // effective privilege for data accesses
val prv = UInt(width = PRV.SZ) // not truly part of mstatus, but convenient
val sd = Bool()
val zero2 = UInt(width = 27)
@ -463,6 +464,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
io.status.isa := reg_misa
io.status.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0)
io.status.sxl := (if (usingVM) log2Ceil(xLen) - 4 else 0)
io.status.dprv := Reg(next = Mux(reg_mstatus.mprv, reg_mstatus.mpp, reg_mstatus.prv))
if (xLen == 32)
io.status.sd_rv32 := io.status.sd