riscv/rocket-chip
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coreplex: support rational crossing to L2 (#534)

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This commit is contained in:
Wesley W. Terpstra
2017-01-27 17:09:43 -08:00
committed by GitHub
parent 61fbe62112
commit 03f2fe02ac
5 changed files with 112 additions and 86 deletions
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24
src/main/scala/rocket/Tile.scala
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@ -73,3 +73,27 @@ class AsyncRocketTile(c: RocketConfig)(implicit p: Parameters) extends LazyModul
rocket.module.io.resetVector := io.resetVector
}
}
class RationalRocketTile(c: RocketConfig)(implicit p: Parameters) extends LazyModule {
val rocket = LazyModule(new RocketTile(c))
val masterNodes = rocket.masterNodes.map(_ => TLRationalOutputNode())
val slaveNode = rocket.slaveNode.map(_ => TLRationalInputNode())
(rocket.masterNodes zip masterNodes) foreach { case (r,n) => n := TLRationalCrossingSource()(r) }
(rocket.slaveNode zip slaveNode) foreach { case (r,n) => r := TLRationalCrossingSink()(n) }
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val master = masterNodes.head.bundleOut // TODO fix after Chisel #366
val slave = slaveNode.map(_.bundleIn)
val hartid = UInt(INPUT, p(XLen))
val interrupts = new TileInterrupts()(p).asInput
val resetVector = UInt(INPUT, p(XLen))
}
rocket.module.io.interrupts := ShiftRegister(io.interrupts, 1)
// signals that do not change:
rocket.module.io.hartid := io.hartid
rocket.module.io.resetVector := io.resetVector
}
}