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coreplex: support rational crossing to L2 (#534)

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This commit is contained in:
Wesley W. Terpstra
2017-01-27 17:09:43 -08:00
committed by GitHub
parent 61fbe62112
commit 03f2fe02ac
5 changed files with 112 additions and 86 deletions
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13
src/main/scala/coreplex/Configs.scala
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@@ -18,6 +18,7 @@ class BaseCoreplexConfig extends Config ((site, here, up) => {
case PAddrBits => 32
case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */
case ASIdBits => 7
case RocketCrossing => Synchronous
//Params used by all caches
case CacheName("L1I") => CacheConfig(
nSets = 64,
@@ -215,3 +216,15 @@ class WithFPUWithoutDivSqrt extends Config((site, here, up) => {
class WithBootROMFile(bootROMFile: String) extends Config((site, here, up) => {
case BootROMFile => bootROMFile
})
class WithSynchronousRocketTiles extends Config((site, here, up) => {
case RocketCrossing => Synchronous
})
class WithAynchronousRocketTiles(depth: Int, sync: Int) extends Config((site, here, up) => {
case RocketCrossing => Asynchronous(depth, sync)
})
class WithRationalRocketTiles extends Config((site, here, up) => {
case RocketCrossing => Rational
})