PUM -> SUM

src/main/scala/rocket/CSR.scala

@@ -30,7 +30,7 @@ class MStatus extends Bundle {
   val tw = Bool()
   val tvm = Bool()
   val mxr = Bool()
-  val pum = Bool()
+  val sum = Bool()
   val mprv = Bool()
   val xs = UInt(width = 2)
   val fs = UInt(width = 2)
@@ -553,7 +553,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
         reg_mstatus.mpp := trimPrivilege(new_mstatus.mpp)
         reg_mstatus.mxr := new_mstatus.mxr
         if (usingVM) {
-          reg_mstatus.pum := new_mstatus.pum
+          reg_mstatus.sum := new_mstatus.sum
           reg_mstatus.spp := new_mstatus.spp
           reg_mstatus.spie := new_mstatus.spie
           reg_mstatus.sie := new_mstatus.sie
@@ -617,7 +617,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
         reg_mstatus.sie := new_sstatus.sie
         reg_mstatus.spie := new_sstatus.spie
         reg_mstatus.spp := new_sstatus.spp
-        reg_mstatus.pum := new_sstatus.pum
+        reg_mstatus.sum := new_sstatus.sum
         reg_mstatus.fs := Fill(2, new_sstatus.fs.orR) // even without an FPU
         if (usingRoCC) reg_mstatus.xs := Fill(2, new_sstatus.xs.orR)
       }

src/main/scala/rocket/PTW.scala

@@ -13,12 +13,7 @@ import util._
 import scala.collection.mutable.ListBuffer
 
 class PTWReq(implicit p: Parameters) extends CoreBundle()(p) {
-  val prv = Bits(width = 2)
-  val pum = Bool()
-  val mxr = Bool()
   val addr = UInt(width = vpnBits)
-  val store = Bool()
-  val fetch = Bool()
 }
 
 class PTWResp(implicit p: Parameters) extends CoreBundle()(p) {

src/main/scala/rocket/TLB.scala

@@ -144,7 +144,7 @@ class TLB(lgMaxSize: Int, entries: Int)(implicit edge: TLEdgeOut, p: Parameters)
   val plru = new PseudoLRU(normalEntries)
   val repl_waddr = Mux(!valid.andR, PriorityEncoder(~valid), plru.replace)
 
-  val priv_ok = Mux(priv_s, ~Mux(io.ptw.status.pum, u_array, UInt(0)), u_array)
+  val priv_ok = Mux(priv_s, ~Mux(io.ptw.status.sum, UInt(0), u_array), u_array)
   val w_array = Cat(prot_w, priv_ok & ~(~prot_w << specialEntry) & sw_array)
   val x_array = Cat(prot_x, priv_ok & ~(~prot_x << specialEntry) & sx_array)
   val r_array = Cat(prot_r, priv_ok & ~(~prot_r << specialEntry) & (sr_array | Mux(io.ptw.status.mxr, xr_array, UInt(0))))
@@ -178,8 +178,6 @@ class TLB(lgMaxSize: Int, entries: Int)(implicit edge: TLEdgeOut, p: Parameters)
   io.ptw.req.valid := state === s_request
   io.ptw.req.bits <> io.ptw.status
   io.ptw.req.bits.addr := r_refill_tag
-  io.ptw.req.bits.store := r_req.store
-  io.ptw.req.bits.fetch := r_req.instruction
 
   if (usingVM) {
     val sfence = io.req.valid && io.req.bits.sfence.valid

src/main/scala/tile/LegacyRoCC.scala

@@ -308,8 +308,6 @@ class TranslatorExample(implicit p: Parameters) extends RoCC()(p) {
 
   ptw.req.valid := (state === s_ptw_req)
   ptw.req.bits.addr := req_vpn
-  ptw.req.bits.store := Bool(false)
-  ptw.req.bits.fetch := Bool(false)
 
   io.resp.valid := (state === s_resp)
   io.resp.bits.rd := req_rd