move replays to writeback stage
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@ -12,6 +12,7 @@ class ioDpathBTB extends Bundle()
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val hit = Bool('output);
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val target = UFix(VADDR_BITS, 'output);
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val wen = Bool('input);
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val clr = Bool('input);
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val correct_pc4 = UFix(VADDR_BITS, 'input);
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val correct_target = UFix(VADDR_BITS, 'input);
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}
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@ -27,13 +28,13 @@ class rocketDpathBTB(entries: Int) extends Component
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val tagmsb = (VADDR_BITS-idxmsb-1)+(VADDR_BITS-idxlsb)-1;
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val taglsb = (VADDR_BITS-idxlsb);
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val rst_lwlr_pf = Mem(entries, io.wen, io.correct_pc4(idxmsb,idxlsb), UFix(1,1), resetVal = UFix(0,1));
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val lwlr_pf = Mem(entries, io.wen, io.correct_pc4(idxmsb,idxlsb),
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Cat(io.correct_pc4(VADDR_BITS-1,idxmsb+1), io.correct_target(VADDR_BITS-1,idxlsb)), resetVal = UFix(0,1));
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val is_val = rst_lwlr_pf(io.current_pc4(idxmsb,idxlsb));
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val tag_target = lwlr_pf(io.current_pc4(idxmsb, idxlsb));
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val vb_array = Mem(entries, io.wen || io.clr, io.correct_pc4(idxmsb,idxlsb), !io.clr, resetVal = Bool(false));
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val tag_target_array = Mem(entries, io.wen, io.correct_pc4(idxmsb,idxlsb),
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Cat(io.correct_pc4(VADDR_BITS-1,idxmsb+1), io.correct_target(VADDR_BITS-1,idxlsb)))
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val is_val = vb_array(io.current_pc4(idxmsb,idxlsb));
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val tag_target = tag_target_array(io.current_pc4(idxmsb, idxlsb));
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io.hit := (is_val & (tag_target(tagmsb,taglsb) === io.current_pc4(VADDR_BITS-1, idxmsb+1))).toBool;
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io.hit := is_val && (tag_target(tagmsb,taglsb) === io.current_pc4(VADDR_BITS-1, idxmsb+1));
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io.target := Cat(tag_target(taglsb-1, 0), Bits(0,idxlsb)).toUFix;
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}
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