riscv/rocket-chip
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This commit is contained in:
Andrew Waterman
2017-09-15 18:41:50 -07:00
parent 9a175b0fb1
commit 034ea722f4
2 changed files with 30 additions and 8 deletions
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src/main/scala/rocket/Frontend.scala
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@ -70,6 +70,7 @@ class FrontendBundle(outer: Frontend) extends CoreBundle()(outer.p)
val ptw = new TLBPTWIO()
val tl_out = outer.masterNode.bundleOut
val tl_in = outer.slaveNode.bundleIn
val errors = new ICacheErrors
}
class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
@ -286,6 +287,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
// performance events
io.cpu.perf := icache.io.perf
io.cpu.perf.tlbMiss := io.ptw.req.fire()
io.errors := icache.io.errors
def alignPC(pc: UInt) = ~(~pc | (coreInstBytes - 1))
}