subsystem: bus wrappers now in BaseSubsystem
This commit is contained in:
parent
b617e26c13
commit
030c6f0206
@ -5,7 +5,7 @@ package freechips.rocketchip.devices.debug
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import Chisel._
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import Chisel._
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import chisel3.core.{IntParam, Input, Output}
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import chisel3.core.{IntParam, Input, Output}
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.subsystem.HasPeripheryBus
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.jtag._
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import freechips.rocketchip.jtag._
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@ -26,12 +26,9 @@ class DebugIO(implicit val p: Parameters) extends ParameterizedBundle()(p) with
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/** Either adds a JTAG DTM to system, and exports a JTAG interface,
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/** Either adds a JTAG DTM to system, and exports a JTAG interface,
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* or exports the Debug Module Interface (DMI), based on a global parameter.
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* or exports the Debug Module Interface (DMI), based on a global parameter.
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*/
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*/
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trait HasPeripheryDebug extends HasPeripheryBus {
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trait HasPeripheryDebug { this: BaseSubsystem =>
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val module: HasPeripheryDebugModuleImp
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val debug = LazyModule(new TLDebugModule(pbus.beatBytes))
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val debug = LazyModule(new TLDebugModule(pbus.beatBytes))
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pbus.toVariableWidthSlave(Some("debug")){ debug.node }
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pbus.toVariableWidthSlave(Some("Debug")){ debug.node }
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}
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}
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trait HasPeripheryDebugBundle {
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trait HasPeripheryDebugBundle {
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@ -4,7 +4,7 @@ package freechips.rocketchip.devices.tilelink
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import Chisel._
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.subsystem.{BaseSubsystem, HasResetVectorWire}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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import freechips.rocketchip.util._
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@ -59,7 +59,7 @@ class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], exec
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}
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}
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/** Adds a boot ROM that contains the DTB describing the system's subsystem. */
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/** Adds a boot ROM that contains the DTB describing the system's subsystem. */
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trait HasPeripheryBootROM extends HasPeripheryBus {
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trait HasPeripheryBootROM { this: BaseSubsystem =>
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val dtb: DTB
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val dtb: DTB
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private val params = p(BootROMParams)
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private val params = p(BootROMParams)
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private lazy val contents = {
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private lazy val contents = {
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@ -71,7 +71,7 @@ trait HasPeripheryBootROM extends HasPeripheryBus {
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val bootrom = LazyModule(new TLROM(params.address, params.size, contents, true, pbus.beatBytes))
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val bootrom = LazyModule(new TLROM(params.address, params.size, contents, true, pbus.beatBytes))
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pbus.toVariableWidthSlave(Some("BootROM")){ bootrom.node }
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pbus.toVariableWidthSlave(Some("bootrom")){ bootrom.node }
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}
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}
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/** Subsystem will power-on running at 0x10040 (BootROM) */
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/** Subsystem will power-on running at 0x10040 (BootROM) */
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@ -4,7 +4,6 @@ package freechips.rocketchip.devices.tilelink
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import Chisel._
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.subsystem.HasPeripheryBus
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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import freechips.rocketchip.util._
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@ -4,7 +4,7 @@ package freechips.rocketchip.devices.tilelink
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import Chisel._
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.subsystem.HasPeripheryBus
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import freechips.rocketchip.subsystem.BaseSubsystem
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.regmapper._
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import freechips.rocketchip.regmapper._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.tilelink._
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@ -91,7 +91,7 @@ class CLINT(params: CLINTParams, beatBytes: Int)(implicit p: Parameters) extends
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}
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}
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/** Trait that will connect a CLINT to a subsystem */
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/** Trait that will connect a CLINT to a subsystem */
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trait HasPeripheryCLINT extends HasPeripheryBus {
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trait HasPeripheryCLINT { this: BaseSubsystem =>
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val clint = LazyModule(new CLINT(p(CLINTKey), pbus.beatBytes))
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val clint = LazyModule(new CLINT(p(CLINTKey), pbus.beatBytes))
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pbus.toVariableWidthSlave(Some("CLINT")) { clint.node }
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pbus.toVariableWidthSlave(Some("clint")) { clint.node }
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}
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}
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@ -4,7 +4,7 @@ package freechips.rocketchip.devices.tilelink
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import Chisel._
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.subsystem.HasSystemBus
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import freechips.rocketchip.subsystem.BaseSubsystem
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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import freechips.rocketchip.util._
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@ -118,7 +118,7 @@ class DeadlockDevice(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parame
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}
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}
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}
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}
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trait HasSystemErrorSlave extends HasSystemBus {
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trait HasSystemErrorSlave { this: BaseSubsystem =>
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private val params = p(ErrorParams)
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private val params = p(ErrorParams)
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val error = LazyModule(new TLError(params, sbus.beatBytes))
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val error = LazyModule(new TLError(params, sbus.beatBytes))
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sbus.toSlave(Some("Error")){ error.node }
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sbus.toSlave(Some("Error")){ error.node }
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@ -3,9 +3,9 @@
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package freechips.rocketchip.devices.tilelink
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package freechips.rocketchip.devices.tilelink
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import Chisel._
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import Chisel._
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import freechips.rocketchip.subsystem.{HasPeripheryBus}
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.subsystem.BaseSubsystem
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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import freechips.rocketchip.util._
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@ -13,7 +13,7 @@ case class MaskROMParams(address: BigInt, name: String, depth: Int = 2048, width
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case object PeripheryMaskROMKey extends Field[Seq[MaskROMParams]]
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case object PeripheryMaskROMKey extends Field[Seq[MaskROMParams]]
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trait HasPeripheryMaskROMSlave extends HasPeripheryBus {
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trait HasPeripheryMaskROMSlave { this: BaseSubsystem =>
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val maskROMParams = p(PeripheryMaskROMKey)
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val maskROMParams = p(PeripheryMaskROMKey)
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val maskROMs = maskROMParams map { params =>
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val maskROMs = maskROMParams map { params =>
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val maskROM = LazyModule(new TLMaskROM(params))
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val maskROM = LazyModule(new TLMaskROM(params))
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@ -5,7 +5,7 @@ package freechips.rocketchip.devices.tilelink
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import Chisel._
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import Chisel._
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import Chisel.ImplicitConversions._
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import Chisel.ImplicitConversions._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.subsystem.{HasInterruptBus, HasPeripheryBus}
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import freechips.rocketchip.subsystem.BaseSubsystem
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.regmapper._
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import freechips.rocketchip.regmapper._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.tilelink._
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@ -269,8 +269,8 @@ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends
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}
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}
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/** Trait that will connect a PLIC to a subsystem */
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/** Trait that will connect a PLIC to a subsystem */
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trait HasPeripheryPLIC extends HasInterruptBus with HasPeripheryBus {
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trait HasPeripheryPLIC { this: BaseSubsystem =>
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val plic = LazyModule(new TLPLIC(p(PLICKey), pbus.beatBytes)))
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val plic = LazyModule(new TLPLIC(p(PLICKey), pbus.beatBytes))
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pbus.toVariableWidthSlave(Some("PLIC")) { plic.node }
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pbus.toVariableWidthSlave(Some("plic")) { plic.node }
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plic.intnode := ibus.toPLIC
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plic.intnode := ibus.toPLIC
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}
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}
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@ -4,7 +4,7 @@ package freechips.rocketchip.devices.tilelink
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import Chisel._
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.subsystem.HasMemoryBus
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import freechips.rocketchip.subsystem.BaseSubsystem
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.tilelink._
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@ -46,20 +46,17 @@ case class ZeroParams(base: Long, size: Long, beatBytes: Int)
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case object ZeroParams extends Field[ZeroParams]
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case object ZeroParams extends Field[ZeroParams]
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/** Adds a /dev/null slave that generates zero-filled responses to reads */
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/** Adds a /dev/null slave that generates zero-filled responses to reads */
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trait HasMemoryZeroSlave extends HasMemoryBus {
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trait HasMemoryZeroSlave { this: BaseSubsystem =>
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private val params = p(ZeroParams)
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private val params = p(ZeroParams)
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private val device = new SimpleDevice("rom", Seq("ucbbar,cacheable-zero0"))
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private val device = new SimpleDevice("rom", Seq("ucbbar,cacheable-zero0"))
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val zeros = memBuses
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val zeros = memBuses.zipWithIndex.map { case (bus, channel) =>
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.map(m => m.toVariableWidthSlave(Some("Zero"))(_))
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.zipWithIndex
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.map { case (attach, channel) =>
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val channels = memBuses.size
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val channels = memBuses.size
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val base = AddressSet(params.base, params.size-1)
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val base = AddressSet(params.base, params.size-1)
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val filter = AddressSet(channel * cacheBlockBytes, ~((channels-1) * cacheBlockBytes))
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val filter = AddressSet(channel * bus.blockBytes, ~((channels-1) * bus.blockBytes))
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val address = base.intersect(filter).get
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val address = base.intersect(filter).get
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val zero = LazyModule(new TLZero(address, beatBytes = params.beatBytes, resources = device.reg("mem")))
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val zero = LazyModule(new TLZero(address, beatBytes = params.beatBytes, resources = device.reg("mem")))
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attach { zero.node }
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bus.toVariableWidthSlave(Some("Zero")) { zero.node }
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zero
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zero
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}
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}
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}
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}
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@ -17,8 +17,7 @@ case object TileId extends Field[Int]
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class GroundTestSubsystem(implicit p: Parameters) extends BaseSubsystem
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class GroundTestSubsystem(implicit p: Parameters) extends BaseSubsystem
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with HasMasterAXI4MemPort
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with HasMasterAXI4MemPort
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with HasPeripheryTestRAMSlave
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with HasPeripheryTestRAMSlave {
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with HasInterruptBus {
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val tileParams = p(GroundTestTilesKey)
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val tileParams = p(GroundTestTilesKey)
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val tiles = tileParams.zipWithIndex.map { case(c, i) => LazyModule(
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val tiles = tileParams.zipWithIndex.map { case(c, i) => LazyModule(
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c.build(i, p.alterPartial {
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c.build(i, p.alterPartial {
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@ -48,13 +47,13 @@ class GroundTestSubsystemModule[+L <: GroundTestSubsystem](_outer: L) extends Ba
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}
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}
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/** Adds a SRAM to the system for testing purposes. */
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/** Adds a SRAM to the system for testing purposes. */
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trait HasPeripheryTestRAMSlave extends HasPeripheryBus {
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trait HasPeripheryTestRAMSlave { this: BaseSubsystem =>
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val testram = LazyModule(new TLRAM(AddressSet(0x52000000, 0xfff), true, true, pbus.beatBytes))
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val testram = LazyModule(new TLRAM(AddressSet(0x52000000, 0xfff), true, true, pbus.beatBytes))
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pbus.toVariableWidthSlave(Some("TestRAM")) { testram.node }
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pbus.toVariableWidthSlave(Some("TestRAM")) { testram.node }
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}
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}
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/** Adds a fuzzing master to the system for testing purposes. */
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/** Adds a fuzzing master to the system for testing purposes. */
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trait HasPeripheryTestFuzzMaster extends HasPeripheryBus {
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trait HasPeripheryTestFuzzMaster { this: BaseSubsystem =>
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val fuzzer = LazyModule(new TLFuzzer(5000))
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val fuzzer = LazyModule(new TLFuzzer(5000))
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pbus.fromOtherMaster(Some("Fuzzer")) { fuzzer.node }
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pbus.fromOtherMaster(Some("Fuzzer")) { fuzzer.node }
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}
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}
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@ -26,15 +26,53 @@ abstract class BareSubsystemModule[+L <: BareSubsystem](_outer: L) extends LazyM
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}
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}
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/** Base Subsystem class with no peripheral devices or ports added */
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/** Base Subsystem class with no peripheral devices or ports added */
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abstract class BaseSubsystem(implicit p: Parameters) extends BareSubsystem
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abstract class BaseSubsystem(implicit p: Parameters) extends BareSubsystem {
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with HasInterruptBus
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with HasSystemBus
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with HasPeripheryBus
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with HasMemoryBus {
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override val module: BaseSubsystemModule[BaseSubsystem]
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override val module: BaseSubsystemModule[BaseSubsystem]
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// These are wrappers around the standard buses available in all subsytems, where
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// peripherals, tiles, ports, and other masters and slaves can attach themselves.
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val ibus = new InterruptBusWrapper()
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val sbus = LazyModule(new SystemBus(p(SystemBusKey)))
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val pbus = LazyModule(new PeripheryBus(p(PeripheryBusKey)))
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val fbus = LazyModule(new FrontBus(p(FrontBusKey)))
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// The sbus masters the pbus; here we convert TL-UH -> TL-UL
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pbus.fromSystemBus() { sbus.toPeripheryBus() { pbus.crossTLIn } }
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// The fbus masters the sbus; both are TL-UH or TL-C
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FlipRendering { implicit p =>
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fbus.toSystemBus() { sbus.fromFrontBus { fbus.crossTLOut } }
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}
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// The sbus masters the mbus; here we convert TL-C -> TL-UH
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private val mbusParams = p(MemoryBusKey)
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private val l2Params = p(BankedL2Key)
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val MemoryBusParams(memBusBeatBytes, memBusBlockBytes) = mbusParams
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val BankedL2Params(nMemoryChannels, nBanksPerChannel, coherenceManager) = l2Params
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val nBanks = l2Params.nBanks
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val cacheBlockBytes = memBusBlockBytes
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// TODO: the below call to coherenceManager should be wrapped in a LazyScope here,
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// but plumbing halt is too annoying for now.
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private val (in, out, halt) = coherenceManager(this)
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def memBusCanCauseHalt: () => Option[Bool] = halt
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require (isPow2(nMemoryChannels) || nMemoryChannels == 0)
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require (isPow2(nBanksPerChannel))
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require (isPow2(memBusBlockBytes))
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private val mask = ~BigInt((nBanks-1) * memBusBlockBytes)
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val memBuses = Seq.tabulate(nMemoryChannels) { channel =>
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val mbus = LazyModule(new MemoryBus(mbusParams)(p))
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for (bank <- 0 until nBanksPerChannel) {
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val offset = (bank * nMemoryChannels) + channel
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ForceFanout(a = true) { implicit p => sbus.toMemoryBus { in } }
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mbus.fromCoherenceManager(None) { TLFilter(TLFilter.Mmask(AddressSet(offset * memBusBlockBytes, mask))) } := out
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}
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mbus
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}
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// Make topManagers an Option[] so as to avoid LM name reflection evaluating it...
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// Make topManagers an Option[] so as to avoid LM name reflection evaluating it...
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lazy val topManagers = Some(ManagerUnification(sharedMemoryTLEdge.manager.managers))
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lazy val topManagers = Some(ManagerUnification(sbus.busView.manager.managers))
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ResourceBinding {
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ResourceBinding {
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val managers = topManagers.get
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val managers = topManagers.get
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val max = managers.flatMap(_.address).map(_.max).max
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val max = managers.flatMap(_.address).map(_.max).max
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@ -61,7 +99,7 @@ abstract class BaseSubsystem(implicit p: Parameters) extends BareSubsystem
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abstract class BaseSubsystemModule[+L <: BaseSubsystem](_outer: L) extends BareSubsystemModule(_outer) {
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abstract class BaseSubsystemModule[+L <: BaseSubsystem](_outer: L) extends BareSubsystemModule(_outer) {
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println("Generated Address Map")
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println("Generated Address Map")
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private val aw = (outer.sharedMemoryTLEdge.bundle.addressBits-1)/4 + 1
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private val aw = (outer.sbus.busView.bundle.addressBits-1)/4 + 1
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private val fmt = s"\t%${aw}x - %${aw}x %c%c%c%c%c %s"
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private val fmt = s"\t%${aw}x - %${aw}x %c%c%c%c%c %s"
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private def collect(path: List[String], value: ResourceValue): List[(String, ResourceAddress)] = {
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private def collect(path: List[String], value: ResourceValue): List[(String, ResourceAddress)] = {
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@ -23,6 +23,7 @@ class BaseSubsystemConfig extends Config ((site, here, up) => {
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case SystemBusKey => SystemBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
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case SystemBusKey => SystemBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
|
||||||
case PeripheryBusKey => PeripheryBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
|
case PeripheryBusKey => PeripheryBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
|
||||||
case MemoryBusKey => MemoryBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
|
case MemoryBusKey => MemoryBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
|
||||||
|
case FrontBusKey => FrontBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
|
||||||
// Additional device Parameters
|
// Additional device Parameters
|
||||||
case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)), maxAtomic=site(XLen)/8, maxTransfer=4096)
|
case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)), maxAtomic=site(XLen)/8, maxTransfer=4096)
|
||||||
case BootROMParams => BootROMParams(contentFileName = "./bootrom/bootrom.img")
|
case BootROMParams => BootROMParams(contentFileName = "./bootrom/bootrom.img")
|
||||||
@ -156,7 +157,7 @@ class WithIncoherentTiles extends Config((site, here, up) => {
|
|||||||
r.copy(master = r.master.copy(cork = Some(true)))
|
r.copy(master = r.master.copy(cork = Some(true)))
|
||||||
}
|
}
|
||||||
case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = { subsystem =>
|
case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = { subsystem =>
|
||||||
val ww = LazyModule(new TLWidthWidget(subsystem.sbusBeatBytes)(subsystem.p))
|
val ww = LazyModule(new TLWidthWidget(subsystem.sbus.beatBytes)(subsystem.p))
|
||||||
(ww.node, ww.node, () => None)
|
(ww.node, ww.node, () => None)
|
||||||
})
|
})
|
||||||
})
|
})
|
||||||
|
@ -45,26 +45,26 @@ trait HasCrossingMethods extends LazyModule with LazyScope
|
|||||||
// TileLink
|
// TileLink
|
||||||
|
|
||||||
def crossTLSyncInOut(out: Boolean)(params: BufferParams = BufferParams.default)(implicit p: Parameters): TLNode = {
|
def crossTLSyncInOut(out: Boolean)(params: BufferParams = BufferParams.default)(implicit p: Parameters): TLNode = {
|
||||||
val node = this { LazyModule(new TLBuffer(params)).node }
|
val sync_xing = this { LazyModule(new TLBuffer(params)).node }
|
||||||
checks = CrossingCheck(out, node, node) :: checks
|
checks = CrossingCheck(out, sync_xing, sync_xing) :: checks
|
||||||
node
|
sync_xing
|
||||||
}
|
}
|
||||||
|
|
||||||
def crossTLAsyncInOut(out: Boolean)(depth: Int = 8, sync: Int = 3)(implicit p: Parameters): TLNode = {
|
def crossTLAsyncInOut(out: Boolean)(depth: Int = 8, sync: Int = 3)(implicit p: Parameters): TLNode = {
|
||||||
lazy val asource = LazyModule(new TLAsyncCrossingSource(sync))
|
lazy val async_xing_source = LazyModule(new TLAsyncCrossingSource(sync))
|
||||||
lazy val asink = LazyModule(new TLAsyncCrossingSink(depth, sync))
|
lazy val async_xing_sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
|
||||||
val source = if (out) this { asource } else asource
|
val source = if (out) this { async_xing_source } else async_xing_source
|
||||||
val sink = if (out) asink else this { asink }
|
val sink = if (out) async_xing_sink else this { async_xing_sink }
|
||||||
sink.node :*=* source.node
|
sink.node :*=* source.node
|
||||||
checks = CrossingCheck(out, source.node, sink.node) :: checks
|
checks = CrossingCheck(out, source.node, sink.node) :: checks
|
||||||
NodeHandle(source.node, sink.node)
|
NodeHandle(source.node, sink.node)
|
||||||
}
|
}
|
||||||
|
|
||||||
def crossTLRationalInOut(out: Boolean)(direction: RationalDirection)(implicit p: Parameters): TLNode = {
|
def crossTLRationalInOut(out: Boolean)(direction: RationalDirection)(implicit p: Parameters): TLNode = {
|
||||||
lazy val rsource = LazyModule(new TLRationalCrossingSource)
|
lazy val rational_xing_source = LazyModule(new TLRationalCrossingSource)
|
||||||
lazy val rsink = LazyModule(new TLRationalCrossingSink(if (out) direction else direction.flip))
|
lazy val rational_xing_sink = LazyModule(new TLRationalCrossingSink(if (out) direction else direction.flip))
|
||||||
val source = if (out) this { rsource } else rsource
|
val source = if (out) this { rational_xing_source } else rational_xing_source
|
||||||
val sink = if (out) rsink else this { rsink }
|
val sink = if (out) rational_xing_sink else this { rational_xing_sink }
|
||||||
sink.node :*=* source.node
|
sink.node :*=* source.node
|
||||||
checks = CrossingCheck(out, source.node, sink.node) :: checks
|
checks = CrossingCheck(out, source.node, sink.node) :: checks
|
||||||
NodeHandle(source.node, sink.node)
|
NodeHandle(source.node, sink.node)
|
||||||
@ -92,16 +92,16 @@ trait HasCrossingMethods extends LazyModule with LazyScope
|
|||||||
// AXI4
|
// AXI4
|
||||||
|
|
||||||
def crossAXI4SyncInOut(out: Boolean)(params: BufferParams = BufferParams.default)(implicit p: Parameters): AXI4Node = {
|
def crossAXI4SyncInOut(out: Boolean)(params: BufferParams = BufferParams.default)(implicit p: Parameters): AXI4Node = {
|
||||||
val node = this { LazyModule(new AXI4Buffer(params)).node }
|
val axi4_sync_xing = this { LazyModule(new AXI4Buffer(params)).node }
|
||||||
checks = CrossingCheck(out, node, node) :: checks
|
checks = CrossingCheck(out, axi4_sync_xing, axi4_sync_xing) :: checks
|
||||||
node
|
axi4_sync_xing
|
||||||
}
|
}
|
||||||
|
|
||||||
def crossAXI4AsyncInOut(out: Boolean)(depth: Int = 8, sync: Int = 3)(implicit p: Parameters): AXI4Node = {
|
def crossAXI4AsyncInOut(out: Boolean)(depth: Int = 8, sync: Int = 3)(implicit p: Parameters): AXI4Node = {
|
||||||
lazy val axi4asource = LazyModule(new AXI4AsyncCrossingSource(sync))
|
lazy val axi4_async_xing_source = LazyModule(new AXI4AsyncCrossingSource(sync))
|
||||||
lazy val axi4asink = LazyModule(new AXI4AsyncCrossingSink(depth, sync))
|
lazy val axi4_async_xing_sink = LazyModule(new AXI4AsyncCrossingSink(depth, sync))
|
||||||
val source = if (out) this { axi4asource } else axi4asource
|
val source = if (out) this { axi4_async_xing_source } else axi4_async_xing_source
|
||||||
val sink = if (out) axi4asink else this { axi4asink }
|
val sink = if (out) axi4_async_xing_sink else this { axi4_async_xing_sink }
|
||||||
sink.node :*=* source.node
|
sink.node :*=* source.node
|
||||||
checks = CrossingCheck(out, source.node, sink.node) :: checks
|
checks = CrossingCheck(out, source.node, sink.node) :: checks
|
||||||
NodeHandle(source.node, sink.node)
|
NodeHandle(source.node, sink.node)
|
||||||
@ -127,30 +127,30 @@ trait HasCrossingMethods extends LazyModule with LazyScope
|
|||||||
// Interrupts
|
// Interrupts
|
||||||
|
|
||||||
def crossIntSyncInOut(out: Boolean)(alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = {
|
def crossIntSyncInOut(out: Boolean)(alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = {
|
||||||
lazy val intssource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
|
lazy val int_sync_xing_source = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
|
||||||
lazy val intssink = LazyModule(new IntSyncCrossingSink(0))
|
lazy val int_sync_xing_sink = LazyModule(new IntSyncCrossingSink(0))
|
||||||
val source = if (out) this { intssource } else intssource
|
val source = if (out) this { int_sync_xing_source } else int_sync_xing_source
|
||||||
val sink = if (out) intssink else this { intssink }
|
val sink = if (out) int_sync_xing_sink else this { int_sync_xing_sink }
|
||||||
sink.node :*=* source.node
|
sink.node :*=* source.node
|
||||||
checks = CrossingCheck(out, source.node, sink.node) :: checks
|
checks = CrossingCheck(out, source.node, sink.node) :: checks
|
||||||
NodeHandle(source.node, sink.node)
|
NodeHandle(source.node, sink.node)
|
||||||
}
|
}
|
||||||
|
|
||||||
def crossIntAsyncInOut(out: Boolean)(sync: Int = 3, alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = {
|
def crossIntAsyncInOut(out: Boolean)(sync: Int = 3, alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = {
|
||||||
lazy val intasource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
|
lazy val int_async_xing_source = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
|
||||||
lazy val intasink = LazyModule(new IntSyncCrossingSink(sync))
|
lazy val int_async_xing_sink = LazyModule(new IntSyncCrossingSink(sync))
|
||||||
val source = if (out) this { intasource } else intasource
|
val source = if (out) this { int_async_xing_source } else int_async_xing_source
|
||||||
val sink = if (out) intasink else this { intasink }
|
val sink = if (out) int_async_xing_sink else this { int_async_xing_sink }
|
||||||
sink.node :*=* source.node
|
sink.node :*=* source.node
|
||||||
checks = CrossingCheck(out, source.node, sink.node) :: checks
|
checks = CrossingCheck(out, source.node, sink.node) :: checks
|
||||||
NodeHandle(source.node, sink.node)
|
NodeHandle(source.node, sink.node)
|
||||||
}
|
}
|
||||||
|
|
||||||
def crossIntRationalInOut(out: Boolean)(alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = {
|
def crossIntRationalInOut(out: Boolean)(alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = {
|
||||||
lazy val intrsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
|
lazy val int_rational_xing_source = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
|
||||||
lazy val intrsink = LazyModule(new IntSyncCrossingSink(1))
|
lazy val int_rational_xing_sink = LazyModule(new IntSyncCrossingSink(1))
|
||||||
val source = if (out) this { intrsource } else intrsource
|
val source = if (out) this { int_rational_xing_source } else int_rational_xing_source
|
||||||
val sink = if (out) intrsink else this { intrsink }
|
val sink = if (out) int_rational_xing_sink else this { int_rational_xing_sink }
|
||||||
sink.node :*=* source.node
|
sink.node :*=* source.node
|
||||||
checks = CrossingCheck(out, source.node, sink.node) :: checks
|
checks = CrossingCheck(out, source.node, sink.node) :: checks
|
||||||
NodeHandle(source.node, sink.node)
|
NodeHandle(source.node, sink.node)
|
||||||
|
@ -43,17 +43,3 @@ class FrontBus(params: FrontBusParams, val crossing: SubsystemClockCrossing = Sy
|
|||||||
to("sbus") { gen :=* TLBuffer(buffer) :=* outwardNode }
|
to("sbus") { gen :=* TLBuffer(buffer) :=* outwardNode }
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/** Provides buses that serve as attachment points,
|
|
||||||
* for use in traits that connect individual devices or external ports.
|
|
||||||
*/
|
|
||||||
trait HasFrontBus extends HasSystemBus {
|
|
||||||
private val frontbusParams = p(FrontBusKey)
|
|
||||||
val frontbusBeatBytes = frontbusParams.beatBytes
|
|
||||||
|
|
||||||
val fbus = LazyModule(new FrontBus(frontbusParams))
|
|
||||||
|
|
||||||
FlipRendering { implicit p =>
|
|
||||||
fbus.toSystemBus() { sbus.fromFrontBus { fbus.crossTLOut } }
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
@ -14,12 +14,13 @@ class ClockedTileInputs(implicit val p: Parameters) extends ParameterizedBundle
|
|||||||
with HasExternallyDrivenTileConstants
|
with HasExternallyDrivenTileConstants
|
||||||
with Clocked
|
with Clocked
|
||||||
|
|
||||||
trait HasTiles extends HasSystemBus {
|
trait HasTiles { this: BaseSubsystem =>
|
||||||
val tiles: Seq[BaseTile]
|
val tiles: Seq[BaseTile]
|
||||||
protected def tileParams: Seq[TileParams] = tiles.map(_.tileParams)
|
protected def tileParams: Seq[TileParams] = tiles.map(_.tileParams)
|
||||||
def nTiles: Int = tileParams.size
|
def nTiles: Int = tileParams.size
|
||||||
def hartIdList: Seq[Int] = tileParams.map(_.hartId)
|
def hartIdList: Seq[Int] = tileParams.map(_.hartId)
|
||||||
def localIntCounts: Seq[Int] = tileParams.map(_.core.nLocalInterrupts)
|
def localIntCounts: Seq[Int] = tileParams.map(_.core.nLocalInterrupts)
|
||||||
|
def sharedMemoryTLEdge = sbus.busView
|
||||||
}
|
}
|
||||||
|
|
||||||
trait HasTilesBundle {
|
trait HasTilesBundle {
|
||||||
|
@ -24,11 +24,6 @@ class InterruptBusWrapper(implicit p: Parameters) {
|
|||||||
def toPLIC: IntOutwardNode = int_bus.intnode
|
def toPLIC: IntOutwardNode = int_bus.intnode
|
||||||
}
|
}
|
||||||
|
|
||||||
trait HasInterruptBus {
|
|
||||||
implicit val p: Parameters
|
|
||||||
val ibus = new InterruptBusWrapper
|
|
||||||
}
|
|
||||||
|
|
||||||
/** Specifies the number of external interrupts */
|
/** Specifies the number of external interrupts */
|
||||||
case object NExtTopInterrupts extends Field[Int](0)
|
case object NExtTopInterrupts extends Field[Int](0)
|
||||||
|
|
||||||
@ -36,7 +31,7 @@ case object NExtTopInterrupts extends Field[Int](0)
|
|||||||
* However, it should not be used directly; instead one of the below
|
* However, it should not be used directly; instead one of the below
|
||||||
* synchronization wiring child traits should be used.
|
* synchronization wiring child traits should be used.
|
||||||
*/
|
*/
|
||||||
abstract trait HasExtInterrupts extends HasInterruptBus {
|
abstract trait HasExtInterrupts { this: BaseSubsystem =>
|
||||||
private val device = new Device with DeviceInterrupts {
|
private val device = new Device with DeviceInterrupts {
|
||||||
def describe(resources: ResourceBindings): Description = {
|
def describe(resources: ResourceBindings): Description = {
|
||||||
Description("soc/external-interrupts", describeInterrupts(resources))
|
Description("soc/external-interrupts", describeInterrupts(resources))
|
||||||
@ -50,7 +45,7 @@ abstract trait HasExtInterrupts extends HasInterruptBus {
|
|||||||
/** This trait should be used if the External Interrupts have NOT
|
/** This trait should be used if the External Interrupts have NOT
|
||||||
* already been synchronized to the Periphery (PLIC) Clock.
|
* already been synchronized to the Periphery (PLIC) Clock.
|
||||||
*/
|
*/
|
||||||
trait HasAsyncExtInterrupts extends HasExtInterrupts {
|
trait HasAsyncExtInterrupts extends HasExtInterrupts { this: BaseSubsystem =>
|
||||||
if (nExtInterrupts > 0) {
|
if (nExtInterrupts > 0) {
|
||||||
ibus.fromAsync := extInterrupts
|
ibus.fromAsync := extInterrupts
|
||||||
}
|
}
|
||||||
@ -59,7 +54,7 @@ trait HasAsyncExtInterrupts extends HasExtInterrupts {
|
|||||||
/** This trait can be used if the External Interrupts have already been synchronized
|
/** This trait can be used if the External Interrupts have already been synchronized
|
||||||
* to the Periphery (PLIC) Clock.
|
* to the Periphery (PLIC) Clock.
|
||||||
*/
|
*/
|
||||||
trait HasSyncExtInterrupts extends HasExtInterrupts {
|
trait HasSyncExtInterrupts extends HasExtInterrupts { this: BaseSubsystem =>
|
||||||
if (nExtInterrupts > 0) {
|
if (nExtInterrupts > 0) {
|
||||||
ibus.fromSync := extInterrupts
|
ibus.fromSync := extInterrupts
|
||||||
}
|
}
|
||||||
|
@ -22,11 +22,11 @@ case object BroadcastKey extends Field(BroadcastParams())
|
|||||||
case class BankedL2Params(
|
case class BankedL2Params(
|
||||||
nMemoryChannels: Int = 1,
|
nMemoryChannels: Int = 1,
|
||||||
nBanksPerChannel: Int = 1,
|
nBanksPerChannel: Int = 1,
|
||||||
coherenceManager: HasMemoryBus => (TLInwardNode, TLOutwardNode, () => Option[Bool]) = { subsystem =>
|
coherenceManager: BaseSubsystem => (TLInwardNode, TLOutwardNode, () => Option[Bool]) = { subsystem =>
|
||||||
implicit val p = subsystem.p
|
implicit val p = subsystem.p
|
||||||
val BroadcastParams(nTrackers, bufferless) = p(BroadcastKey)
|
val BroadcastParams(nTrackers, bufferless) = p(BroadcastKey)
|
||||||
val bh = LazyModule(new TLBroadcast(subsystem.memBusBlockBytes, nTrackers, bufferless))
|
val bh = LazyModule(new TLBroadcast(subsystem.memBusBlockBytes, nTrackers, bufferless))
|
||||||
val ww = LazyModule(new TLWidthWidget(subsystem.sbusBeatBytes))
|
val ww = LazyModule(new TLWidthWidget(subsystem.sbus.beatBytes))
|
||||||
ww.node :*= bh.node
|
ww.node :*= bh.node
|
||||||
(bh.node, ww.node, () => None)
|
(bh.node, ww.node, () => None)
|
||||||
}) {
|
}) {
|
||||||
@ -72,29 +72,3 @@ class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWr
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
trait HasMemoryBus extends HasSystemBus with HasPeripheryBus with HasInterruptBus {
|
|
||||||
private val mbusParams = p(MemoryBusKey)
|
|
||||||
private val l2Params = p(BankedL2Key)
|
|
||||||
val MemoryBusParams(memBusBeatBytes, memBusBlockBytes) = mbusParams
|
|
||||||
val BankedL2Params(nMemoryChannels, nBanksPerChannel, coherenceManager) = l2Params
|
|
||||||
val nBanks = l2Params.nBanks
|
|
||||||
val cacheBlockBytes = memBusBlockBytes
|
|
||||||
private val (in, out, halt) = coherenceManager(this)
|
|
||||||
def memBusCanCauseHalt: () => Option[Bool] = halt
|
|
||||||
|
|
||||||
require (isPow2(nMemoryChannels) || nMemoryChannels == 0)
|
|
||||||
require (isPow2(nBanksPerChannel))
|
|
||||||
require (isPow2(memBusBlockBytes))
|
|
||||||
|
|
||||||
private val mask = ~BigInt((nBanks-1) * memBusBlockBytes)
|
|
||||||
val memBuses = Seq.tabulate(nMemoryChannels) { channel =>
|
|
||||||
val mbus = LazyModule(new MemoryBus(mbusParams))
|
|
||||||
for (bank <- 0 until nBanksPerChannel) {
|
|
||||||
val offset = (bank * nMemoryChannels) + channel
|
|
||||||
ForceFanout(a = true) { implicit p => sbus.toMemoryBus { in } }
|
|
||||||
mbus.fromCoherenceManager(None) { TLFilter(TLFilter.Mmask(AddressSet(offset * memBusBlockBytes, mask))) } := out
|
|
||||||
}
|
|
||||||
mbus
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
@ -107,16 +107,3 @@ class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCross
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/** Provides buses that serve as attachment points,
|
|
||||||
* for use in traits that connect individual devices or external ports.
|
|
||||||
*/
|
|
||||||
trait HasPeripheryBus extends HasSystemBus {
|
|
||||||
private val pbusParams = p(PeripheryBusKey)
|
|
||||||
val pbusBeatBytes = pbusParams.beatBytes
|
|
||||||
|
|
||||||
val pbus = LazyModule(new PeripheryBus(pbusParams))
|
|
||||||
|
|
||||||
// The peripheryBus hangs off of systemBus; here we convert TL-UH -> TL-UL
|
|
||||||
pbus.fromSystemBus() { sbus.toPeripheryBus() { pbus.crossTLIn } }
|
|
||||||
}
|
|
||||||
|
@ -27,12 +27,13 @@ case object ExtIn extends Field[SlavePortParams]
|
|||||||
///// The following traits add ports to the sytem, in some cases converting to different interconnect standards
|
///// The following traits add ports to the sytem, in some cases converting to different interconnect standards
|
||||||
|
|
||||||
/** Adds a port to the system intended to master an AXI4 DRAM controller. */
|
/** Adds a port to the system intended to master an AXI4 DRAM controller. */
|
||||||
trait HasMasterAXI4MemPort extends HasMemoryBus {
|
trait HasMasterAXI4MemPort { this: BaseSubsystem =>
|
||||||
val module: HasMasterAXI4MemPortModuleImp
|
val module: HasMasterAXI4MemPortModuleImp
|
||||||
|
|
||||||
private val params = p(ExtMem)
|
private val params = p(ExtMem)
|
||||||
private val portName = "axi4"
|
private val portName = "axi4"
|
||||||
private val device = new MemoryDevice
|
private val device = new MemoryDevice
|
||||||
|
val nMemoryChannels: Int
|
||||||
|
|
||||||
val mem_axi4 = AXI4SlaveNode(Seq.tabulate(nMemoryChannels) { channel =>
|
val mem_axi4 = AXI4SlaveNode(Seq.tabulate(nMemoryChannels) { channel =>
|
||||||
val base = AddressSet(params.base, params.size-1)
|
val base = AddressSet(params.base, params.size-1)
|
||||||
@ -73,13 +74,14 @@ trait HasMasterAXI4MemPortBundle {
|
|||||||
/** Actually generates the corresponding IO in the concrete Module */
|
/** Actually generates the corresponding IO in the concrete Module */
|
||||||
trait HasMasterAXI4MemPortModuleImp extends LazyModuleImp with HasMasterAXI4MemPortBundle {
|
trait HasMasterAXI4MemPortModuleImp extends LazyModuleImp with HasMasterAXI4MemPortBundle {
|
||||||
val outer: HasMasterAXI4MemPort
|
val outer: HasMasterAXI4MemPort
|
||||||
|
|
||||||
val mem_axi4 = IO(HeterogeneousBag.fromNode(outer.mem_axi4.in))
|
val mem_axi4 = IO(HeterogeneousBag.fromNode(outer.mem_axi4.in))
|
||||||
(mem_axi4 zip outer.mem_axi4.in) foreach { case (i, (o, _)) => i <> o }
|
(mem_axi4 zip outer.mem_axi4.in) foreach { case (i, (o, _)) => i <> o }
|
||||||
val nMemoryChannels = outer.nMemoryChannels
|
val nMemoryChannels = outer.nMemoryChannels
|
||||||
}
|
}
|
||||||
|
|
||||||
/** Adds a AXI4 port to the system intended to master an MMIO device bus */
|
/** Adds a AXI4 port to the system intended to master an MMIO device bus */
|
||||||
trait HasMasterAXI4MMIOPort extends HasSystemBus {
|
trait HasMasterAXI4MMIOPort { this: BaseSubsystem =>
|
||||||
private val params = p(ExtBus)
|
private val params = p(ExtBus)
|
||||||
private val portName = "mmio_port_axi4"
|
private val portName = "mmio_port_axi4"
|
||||||
private val device = new SimpleBus(portName.kebab, Nil)
|
private val device = new SimpleBus(portName.kebab, Nil)
|
||||||
@ -119,7 +121,7 @@ trait HasMasterAXI4MMIOPortModuleImp extends LazyModuleImp with HasMasterAXI4MMI
|
|||||||
}
|
}
|
||||||
|
|
||||||
/** Adds an AXI4 port to the system intended to be a slave on an MMIO device bus */
|
/** Adds an AXI4 port to the system intended to be a slave on an MMIO device bus */
|
||||||
trait HasSlaveAXI4Port extends HasSystemBus {
|
trait HasSlaveAXI4Port { this: BaseSubsystem =>
|
||||||
private val params = p(ExtIn)
|
private val params = p(ExtIn)
|
||||||
private val portName = "slave_port_axi4"
|
private val portName = "slave_port_axi4"
|
||||||
val l2FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
|
val l2FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
|
||||||
@ -160,7 +162,7 @@ trait HasSlaveAXI4PortModuleImp extends LazyModuleImp with HasSlaveAXI4PortBundl
|
|||||||
}
|
}
|
||||||
|
|
||||||
/** Adds a TileLink port to the system intended to master an MMIO device bus */
|
/** Adds a TileLink port to the system intended to master an MMIO device bus */
|
||||||
trait HasMasterTLMMIOPort extends HasSystemBus {
|
trait HasMasterTLMMIOPort { this: BaseSubsystem =>
|
||||||
private val params = p(ExtBus)
|
private val params = p(ExtBus)
|
||||||
private val portName = "mmio_port_tl"
|
private val portName = "mmio_port_tl"
|
||||||
private val device = new SimpleBus(portName.kebab, Nil)
|
private val device = new SimpleBus(portName.kebab, Nil)
|
||||||
@ -204,7 +206,7 @@ trait HasMasterTLMMIOPortModuleImp extends LazyModuleImp with HasMasterTLMMIOPor
|
|||||||
/** Adds an TL port to the system intended to be a slave on an MMIO device bus.
|
/** Adds an TL port to the system intended to be a slave on an MMIO device bus.
|
||||||
* NOTE: this port is NOT allowed to issue Acquires.
|
* NOTE: this port is NOT allowed to issue Acquires.
|
||||||
*/
|
*/
|
||||||
trait HasSlaveTLPort extends HasSystemBus {
|
trait HasSlaveTLPort { this: BaseSubsystem =>
|
||||||
private val params = p(ExtIn)
|
private val params = p(ExtIn)
|
||||||
private val portName = "slave_port_tl"
|
private val portName = "slave_port_tl"
|
||||||
val l2FrontendTLNode = TLClientNode(Seq(TLClientPortParameters(
|
val l2FrontendTLNode = TLClientNode(Seq(TLClientPortParameters(
|
||||||
|
@ -7,7 +7,7 @@ import freechips.rocketchip.diplomacy.{LazyModuleImp, DTSTimebase}
|
|||||||
import freechips.rocketchip.devices.tilelink.HasPeripheryCLINT
|
import freechips.rocketchip.devices.tilelink.HasPeripheryCLINT
|
||||||
|
|
||||||
trait HasRTCModuleImp extends LazyModuleImp {
|
trait HasRTCModuleImp extends LazyModuleImp {
|
||||||
val outer: HasPeripheryCLINT
|
val outer: BaseSubsystem with HasPeripheryCLINT
|
||||||
private val pbusFreq = outer.p(PeripheryBusKey).frequency
|
private val pbusFreq = outer.p(PeripheryBusKey).frequency
|
||||||
private val rtcFreq = outer.p(DTSTimebase)
|
private val rtcFreq = outer.p(DTSTimebase)
|
||||||
private val internalPeriod: BigInt = pbusFreq / rtcFreq
|
private val internalPeriod: BigInt = pbusFreq / rtcFreq
|
||||||
|
@ -31,10 +31,9 @@ case object RocketTilesKey extends Field[Seq[RocketTileParams]](Nil)
|
|||||||
case object RocketCrossingKey extends Field[Seq[RocketCrossingParams]](List(RocketCrossingParams()))
|
case object RocketCrossingKey extends Field[Seq[RocketCrossingParams]](List(RocketCrossingParams()))
|
||||||
|
|
||||||
trait HasRocketTiles extends HasTiles
|
trait HasRocketTiles extends HasTiles
|
||||||
with HasPeripheryBus
|
|
||||||
with HasPeripheryPLIC
|
with HasPeripheryPLIC
|
||||||
with HasPeripheryCLINT
|
with HasPeripheryCLINT
|
||||||
with HasPeripheryDebug {
|
with HasPeripheryDebug { this: BaseSubsystem =>
|
||||||
val module: HasRocketTilesModuleImp
|
val module: HasRocketTilesModuleImp
|
||||||
|
|
||||||
protected val rocketTileParams = p(RocketTilesKey)
|
protected val rocketTileParams = p(RocketTilesKey)
|
||||||
@ -104,7 +103,7 @@ trait HasRocketTiles extends HasTiles
|
|||||||
.map { BasicBusBlockerParams(_, pbus.beatBytes, sbus.beatBytes) }
|
.map { BasicBusBlockerParams(_, pbus.beatBytes, sbus.beatBytes) }
|
||||||
.map { bbbp => LazyModule(new BasicBusBlocker(bbbp)) }
|
.map { bbbp => LazyModule(new BasicBusBlocker(bbbp)) }
|
||||||
.map { bbb =>
|
.map { bbb =>
|
||||||
pbus.toVariableWidthSlave(Some("TileSlavePortBusBlocker")) { bbb.controlNode }
|
pbus.toVariableWidthSlave(Some("bus_blocker")) { bbb.controlNode }
|
||||||
rocket.crossTLIn :*= bbb.node
|
rocket.crossTLIn :*= bbb.node
|
||||||
} .getOrElse { rocket.crossTLIn }
|
} .getOrElse { rocket.crossTLIn }
|
||||||
}
|
}
|
||||||
|
@ -96,15 +96,3 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/** Provides buses that serve as attachment points,
|
|
||||||
* for use in traits that connect individual devices or external ports.
|
|
||||||
*/
|
|
||||||
trait HasSystemBus extends HasInterruptBus {
|
|
||||||
private val sbusParams = p(SystemBusKey)
|
|
||||||
val sbusBeatBytes = sbusParams.beatBytes
|
|
||||||
|
|
||||||
val sbus = LazyModule(new SystemBus(sbusParams))
|
|
||||||
|
|
||||||
def sharedMemoryTLEdge: TLEdge = sbus.busView
|
|
||||||
}
|
|
||||||
|
Loading…
Reference in New Issue
Block a user