riscv/rocket-chip
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subsystem: bus wrappers now in BaseSubsystem

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This commit is contained in:
Henry Cook
2018-02-20 17:10:16 -08:00
parent b617e26c13
commit 030c6f0206
21 changed files with 119 additions and 156 deletions
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3
src/main/scala/subsystem/Configs.scala
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@ -23,6 +23,7 @@ class BaseSubsystemConfig extends Config ((site, here, up) => {
case SystemBusKey => SystemBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
case PeripheryBusKey => PeripheryBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
case MemoryBusKey => MemoryBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
case FrontBusKey => FrontBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
// Additional device Parameters
case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)), maxAtomic=site(XLen)/8, maxTransfer=4096)
case BootROMParams => BootROMParams(contentFileName = "./bootrom/bootrom.img")
@ -156,7 +157,7 @@ class WithIncoherentTiles extends Config((site, here, up) => {
r.copy(master = r.master.copy(cork = Some(true)))
}
case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = { subsystem =>
val ww = LazyModule(new TLWidthWidget(subsystem.sbusBeatBytes)(subsystem.p))
val ww = LazyModule(new TLWidthWidget(subsystem.sbus.beatBytes)(subsystem.p))
(ww.node, ww.node, () => None)
})
})