riscv/rocket-chip
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subsystem: bus wrappers now in BaseSubsystem

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This commit is contained in:
Henry Cook
2018-02-20 17:10:16 -08:00
parent b617e26c13
commit 030c6f0206
21 changed files with 119 additions and 156 deletions
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13
src/main/scala/devices/tilelink/Zero.scala
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@ -4,7 +4,7 @@ package freechips.rocketchip.devices.tilelink
import Chisel._
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.subsystem.HasMemoryBus
import freechips.rocketchip.subsystem.BaseSubsystem
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
@ -46,20 +46,17 @@ case class ZeroParams(base: Long, size: Long, beatBytes: Int)
case object ZeroParams extends Field[ZeroParams]
/** Adds a /dev/null slave that generates zero-filled responses to reads */
trait HasMemoryZeroSlave extends HasMemoryBus {
trait HasMemoryZeroSlave { this: BaseSubsystem =>
private val params = p(ZeroParams)
private val device = new SimpleDevice("rom", Seq("ucbbar,cacheable-zero0"))
val zeros = memBuses
.map(m => m.toVariableWidthSlave(Some("Zero"))(_))
.zipWithIndex
.map { case (attach, channel) =>
val zeros = memBuses.zipWithIndex.map { case (bus, channel) =>
val channels = memBuses.size
val base = AddressSet(params.base, params.size-1)
val filter = AddressSet(channel * cacheBlockBytes, ~((channels-1) * cacheBlockBytes))
val filter = AddressSet(channel * bus.blockBytes, ~((channels-1) * bus.blockBytes))
val address = base.intersect(filter).get
val zero = LazyModule(new TLZero(address, beatBytes = params.beatBytes, resources = device.reg("mem")))
attach { zero.node }
bus.toVariableWidthSlave(Some("Zero")) { zero.node }
zero
}
}