riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

subsystem: bus wrappers now in BaseSubsystem

Browse Source
This commit is contained in:
Henry Cook
2018-02-20 17:10:16 -08:00
parent b617e26c13
commit 030c6f0206
21 changed files with 119 additions and 156 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/main/scala/devices/tilelink/Plic.scala
View File

@ -5,7 +5,7 @@ package freechips.rocketchip.devices.tilelink
import Chisel._
import Chisel.ImplicitConversions._
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.subsystem.{HasInterruptBus, HasPeripheryBus}
import freechips.rocketchip.subsystem.BaseSubsystem
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
@ -269,8 +269,8 @@ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends
}
/** Trait that will connect a PLIC to a subsystem */
trait HasPeripheryPLIC extends HasInterruptBus with HasPeripheryBus {
val plic = LazyModule(new TLPLIC(p(PLICKey), pbus.beatBytes)))
pbus.toVariableWidthSlave(Some("PLIC")) { plic.node }
trait HasPeripheryPLIC { this: BaseSubsystem =>
val plic = LazyModule(new TLPLIC(p(PLICKey), pbus.beatBytes))
pbus.toVariableWidthSlave(Some("plic")) { plic.node }
plic.intnode := ibus.toPLIC
}