riscv/rocket-chip
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subsystem: bus wrappers now in BaseSubsystem

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Henry Cook committed 2018-02-21 14:52:59 -08:00
1 parent b617e26c13
commit 030c6f0206
21 files changed
+119 -156
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src/main/scala/devices/tilelink/Plic.scala
+4 -4
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@@ -5,7 +5,7 @@ package freechips.rocketchip.devices.tilelink
import Chisel._
import Chisel.ImplicitConversions._
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.subsystem.{HasInterruptBus, HasPeripheryBus}
import freechips.rocketchip.subsystem.BaseSubsystem
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
@@ -269,8 +269,8 @@ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends
}
/** Trait that will connect a PLIC to a subsystem */
trait HasPeripheryPLIC extends HasInterruptBus with HasPeripheryBus {
val plic = LazyModule(new TLPLIC(p(PLICKey), pbus.beatBytes)))
pbus.toVariableWidthSlave(Some("PLIC")) { plic.node }
trait HasPeripheryPLIC { this: BaseSubsystem =>
val plic = LazyModule(new TLPLIC(p(PLICKey), pbus.beatBytes))
pbus.toVariableWidthSlave(Some("plic")) { plic.node }
plic.intnode := ibus.toPLIC
}